Jiang Hu - RankMe

300 papers A* 28A 54B 4C 10Misc 4Journal 97Unranked 96

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A New Approach to Performance-Driven Analog IC Placement. ISPD Donghao Fang, Hailiang Hu, Wuxi Li, Jiang Hu
2026	—	`conf`	AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter Tuner. ISPD Runzhi Wang, Jingyu Pan, Yiran Chen, Jiang Hu
2026	—	`conf`	Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language. ASP-DAC Runzhi Wang, Prianka Sengupta, Cristhian Roman-Vicharra, Yiran Chen, Jiang Hu
2025	J	`jnl`	A Survey of Research in Large Language Models for Electronic Design Automation. CoRR Jingyu Pan, Guanglei Zhou, Chen-Chia Chang, Isaac Jacobson, Jiang Hu, Yiran Chen
2025	J	`jnl`	A Survey of Research in Large Language Models for Electronic Design Automation. ACM Trans. Design Autom. Electr. Syst. Jingyu Pan, Guanglei Zhou, Chen-Chia Chang, Isaac Jacobson, Jiang Hu, Yiran Chen
2025	—	`conf`	BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis. MLCAD Surya Jasper, Minh Luu, Evan Pan, Aakash Tyagi, Michael Quinn, Jiang Hu, David Kebo Houngninou
2025	J	`jnl`	BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis. CoRR Surya Jasper, Minh Luu, Evan Pan, Aakash Tyagi, Michael Quinn, Jiang Hu, David Kebo Houngninou
2025	A*	`conf`	Crane: Inter-Layer Scheduling Framework for DNN Inference and Training Co-Support on Tiled Architecture. MICRO Yu Gong, Lingyi Huang, Haodong Chang, Rongjian Liang, Cheng Yang, Zhexiang Tang, Jiang Hu, Bo Yuan
2025	J	`jnl`	DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianfeng Song, Rongjian Liang, Bo Yuan, Jiang Hu
2025	J	`jnl`	Estimating CPI Stacks From Multiplexed Performance Counter Data Using Machine Learning. IEEE Comput. Archit. Lett. Daniel Puckett, Tyler Tomer, Paul V. Gratz, Jiang Hu, Galen M. Shipman, Jered Dominguez-Trujillo, Kevin Sheridan
2025	—	`conf`	FPGA-Based Acceleration for EMT Simulation of Electrical Distribution Network. ASAP Zhenrui Wang, Jiang Hu, Weiping Shi
2025	J	`jnl`	Global Placement Exploiting Soft 2D Regularity. ACM Trans. Design Autom. Electr. Syst. Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu
2025	—	`conf`	Improving Last-Mile Coverage in Functional Verification. MLCAD Chengjia Liu, Jnana Preeti Parlapalli, David Kebo Houngninou, Michael Quinn, Aakash Tyagi, Jiang Hu
2025	—	`conf`	Invited: Physical Design for Systolic Array-Based Integrated Circuits. ISPD Jiang Hu
2025	—	`conf`	Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research. ISPD Vidya A. Chhabria, Jiang Hu, Andrew B. Kahng, Sachin S. Sapatnekar
2025	J	`jnl`	Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language. CoRR Runzhi Wang, Prianka Sengupta, Yiran Chen, Jiang Hu
2025	J	`jnl`	PPAC Driven Multi-die and Multi-technology Floorplanning. CoRR Cristhian Roman-Vicharra, Yiran Chen, Jiang Hu
2025	—	`conf`	PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. ASP-DAC Chen-Chia Chang, Wan-Hsuan Lin, Jingyu Pan, Guanglei Zhou, Zhiyao Xie, Jiang Hu, Yiran Chen
2025	A*	`conf`	PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting. DAC Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Chen-Chia Chang, Jingyu Pan, Jiang Hu, Yiran Chen, Dipto G. Thakurta
2025	J	`jnl`	Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization. CoRR Fenghua Wu, Evan Pan, Rahul Kande, Michael Quinn, Aakash Tyagi, David Kebo Houngninou, Jeyavijayan Rajendran, Jiang Hu
2025	—	`conf`	VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration. MLCAD Minh Luu, Surya Jasper, Khoi Le, Evan Pan, Michael Quinn, Aakash Tyagi, Jiang Hu
2025	J	`jnl`	VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration. CoRR Minh Luu, Surya Jasper, Khoi Le, Evan Pan, Michael Quinn, Aakash Tyagi, Jiang Hu
2024	B	`conf`	Aiding Microprocessor Performance Validation with Machine Learning. ISPASS Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu
2024	A	`conf`	DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture. DATE Jianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan, Jiang Hu
2024	—	`conf`	Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. MLCAD Cristhian Roman-Vicharra, Yiran Chen, Jiang Hu
2024	J	`jnl`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2024	—	`conf`	MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network. MLCAD Prianka Sengupta, Aakash Tyagi, Jiang Hu, Vivek K. Rajan, Hesham Mostafa, Somdeb Majumdar
2024	J	`jnl`	PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques. CoRR Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Jiang Hu, Yiran Chen, Dipto G. Thakurta
2024	—	`ed.`	Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, MLCAD 2024, Salt Lake City, UT, USA, September 9-11, 2024 MLCAD Hussam Amrouch, Jiang Hu, Siddharth Garg, Yibo Lin
2024	A	`conf`	SysMix: Mixed-Size Placement for Systolic-Array-Based Hierarchical Designs. ICCAD Donghao Fang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu
2024	J	`jnl`	Toward Fully Automated Machine Learning for Routability Estimator Development. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Tunhou Zhang, Jiang Hu, Yiran Chen
2023	—	`conf`	BufFormer: A Generative ML Framework for Scalable Buffering. ASP-DAC Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren
2023	—	`conf`	Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction. MLCAD Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu
2023	—	`conf`	Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. ASP-DAC Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen
2023	J	`jnl`	GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2023	A	`conf`	Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff. ICCAD Jiang Hu, Andrew B. Kahng
2023	—	`conf`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops. ISVLSI Chunkai Fu, Ben Trombley, Hua Xiang, Gi-Joon Nam, Jiang Hu
2023	J	`jnl`	Machine Learning for Microprocessor Performance Bug Localization. CoRR Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu
2023	J	`jnl`	Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. ASP-DAC Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen
2023	A	`conf`	Scaled Population Division for Approximate Computing. ISLPED Kunal Bharathi, Sunil P. Khatri, Jiang Hu
2023	J	`jnl`	Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. CoRR Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu
2023	Misc	`conf`	Special Session: Machine Learning for Embedded System Design. CODES+ISSS Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu
2023	A	`conf`	Systolic Array Placement on FPGAs. ICCAD Hailiang Hu, Donghao Fang, Wuxi Li, Bo Yuan, Jiang Hu
2023	J	`jnl`	The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyao Xie, Jingyu Pan, Chen-Chia Chang, Jiang Hu, Yiran Chen
2022	A	`conf`	A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. ICCAD Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam
2022	A	`conf`	Are Analytical Techniques Worthwhile for Analog IC Placement? DATE Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	A	`conf`	DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. ICCAD Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu
2022	A	`conf`	Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow. ICCAD Rongjian Liang, Jianfeng Song, Bo Yuan, Jiang Hu
2022	J	`jnl`	Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2022	—	`conf`	Double Deep Q-Learning Based Irrigation and Chemigation Control. ISQED Jianfeng Song, Dana Porter, Jiang Hu, Thomas H. Marek
2022	—	`conf`	Global Placement Exploiting Soft 2D Regularity. ISPD Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu
2022	A	`conf`	How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. ICCAD Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu
2022	—	`conf`	Machine-Learning Based Delay Prediction for FPGA Technology Mapping. SLIP Hailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, Ismail Bustany
2022	—	`conf`	Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines. ASP-DAC Yishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu
2022	J	`jnl`	Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Chen-Chia Chang, Jingyu Pan, Yiran Chen
2022	A	`conf`	Robustify ML-Based Lithography Hotspot Detectors. ICCAD Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen
2022	B	`conf`	TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. FPL Chan-Wei Hu, Jiang Hu, Sunil P. Khatri
2022	J	`jnl`	Toward Taming the Overhead Monster for Data-flow Integrity. ACM Trans. Design Autom. Electr. Syst. Lang Feng, Jiayi Huang, Jeff Huang, Jiang Hu
2022	J	`jnl`	Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data. CoRR Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen
2022	J	`jnl`	Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Trans. Emerg. Top. Comput. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2022	A*	`conf`	Towards collaborative intelligence: routability estimation based on decentralized private data. DAC Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen
2022	—	`conf`	Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors. ISQED Saumil Gogri, Aakash Tyagi, Michael Quinn, Jiang Hu
2021	—	`conf`	A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2021	J	`jnl`	ALIGN: A System for Automating Analog Layout. IEEE Des. Test Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A*	`conf`	APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das
2021	A	`conf`	Analog Layout Generation using Optimized Primitives. DATE Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani
2021	J	`jnl`	Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio
2021	A*	`conf`	Automatic Microprocessor Performance Bug Detection. HPCA Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu
2021	A	`conf`	Automatic Routability Predictor Development Using Neural Architecture Search. ICCAD Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen
2021	—	`conf`	Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2021	J	`jnl`	FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation. ACM Trans. Design Autom. Electr. Syst. Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy
2021	A	`conf`	FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. ICCAD Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	—	`conf`	Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. ASP-DAC Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen
2021	J	`jnl`	SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Farhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar
2021	J	`jnl`	Toward Taming the Overhead Monster for Data-Flow Integrity. CoRR Lang Feng, Jiayi Huang, Jeff Huang, Jiang Hu
2020	A	`conf`	A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	J	`jnl`	ALIGN: A System for Automating Analog Layout. CoRR Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
2020	J	`jnl`	Automatic Microprocessor Performance Bug Detection. CoRR Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu
2020	J	`jnl`	Automatic Routability Predictor Development Using Neural Architecture Search. CoRR Jingyu Pan, Chen-Chia Chang, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen
2020	J	`jnl`	Breaking Analog Locking Techniques. IEEE Trans. Very Large Scale Integr. Syst. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2020	—	`conf`	DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. ISPD Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi N. Reddy, Shyam Ramji, Gi-Joon Nam, Jiang Hu
2020	—	`conf`	Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation. ASP-DAC Chaofei Yang, Hai Li, Yiran Chen, Jiang Hu
2020	—	`conf`	Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	—	`conf`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	J	`jnl`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	A	`conf`	Fast IR Drop Estimation with Machine Learning : Invited Paper. ICCAD Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen
2020	J	`jnl`	Fast IR Drop Estimation with Machine Learning. CoRR Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen
2020	A	`conf`	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020	—	`conf`	How Much Does Regularity Help FPGA Placement? FPT Hongxin Kong, Lang Feng, Chunhua Deng, Bo Yuan, Jiang Hu
2020	—	`conf`	Learning from Experience: Applying ML to Analog Circuit Design. ISPD Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
2020	J	`jnl`	Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. CoRR Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, Yiran Chen
2020	J	`jnl`	Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng Zhuo, Shaoheng Luo, Houle Gan, Jiang Hu, Zhiguo Shi
2020	—	`conf`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. ASP-DAC Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	J	`jnl`	PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. CoRR Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen
2020	A	`conf`	Routing-Free Crosstalk Prediction. ICCAD Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam
2020	—	`conf`	Scaled Population Arithmetic for Efficient Stochastic Computing. ASP-DAC He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu
2020	C	`conf`	Scaled Population Subtraction for Approximate Computing. ICCD Kunal Bharathi, Jiang Hu, Sunil P. Khatri
2020	A	`conf`	Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. ITC Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Sir Yee Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2019	A*	`conf`	A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. DAC He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu
2019	A*	`conf`	ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2019	J	`jnl`	An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar
2019	A	`conf`	Breaking Analog Locking Techniques via Satisfiability Modulo Theories. ITC Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2019	J	`jnl`	Dynamic Approximation of JPEG Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2019	J	`jnl`	EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grace Li Zhang, Bing Li, Yiyu Shi, Jiang Hu, Ulf Schlichtmann
2019	—	`ch.`	Error Analysis and Optimization in Approximate Arithmetic Circuits. Approximate Circuits Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2019	—	`conf`	Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. ISQED Chaofan Li, Sachin S. Sapatnekar, Jiang Hu
2019	B	`conf`	FastCFI: Real-Time Control Flow Integrity Using FPGA Without Code Instrumentation. RV Lang Feng, Jeff Huang, Jiang Hu, Abhijith Reddy
2019	B	`conf`	Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. RTCSA Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu
2019	—	`conf`	Layout recognition attacks on split manufacturing. ASP-DAC Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu
2019	A*	`conf`	Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism. DAC Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu
2019	A	`conf`	Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
2019	—	`conf`	SeFAct: selective feature activation and early classification for CNNs. ASP-DAC Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar
2018	J	`jnl`	A Built-In Self-Test and In Situ Analog Circuit Optimization Platform. IEEE Trans. Circuits Syst. I Regul. Pap. Sanghoon Lee, Congyin Shi, Jiafan Wang, Adriana C. Sanabria-Borbon, Hatem Osman, Jiang Hu, Edgar Sánchez-Sinencio
2018	J	`jnl`	A Simple Yet Efficient Accuracy-Configurable Adder Design. IEEE Trans. Very Large Scale Integr. Syst. Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu
2018	—	`conf`	DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network Communication. ICVES Hongxin Kong, Jun Cheng, Krishna R. Narayanan, Jiang Hu
2018	—	`conf`	Exploring Serverless Computing for Neural Network Training. IEEE CLOUD Lang Feng, Prabhakar Kudva, Dilma Da Silva, Jiang Hu
2018	Misc	`conf`	Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. RTNS Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu
2018	—	`conf`	Interconnect Optimization Considering Multiple Critical Paths. ISPD Jiang Hu, Ying Zhou, Yaoguang Wei, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Téllez, Gi-Joon Nam
2018	A	`conf`	RouteNet: routability prediction for mixed-size designs using convolutional neural network. ICCAD Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
2018	J	`jnl`	The Cat and Mouse in Split Manufacturing. IEEE Trans. Very Large Scale Integr. Syst. Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran
2018	J	`jnl`	Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IACR Cryptol. ePrint Arch. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2018	A	`conf`	Towards provably-secure analog and mixed-signal locking against overproduction. ICCAD Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2018	A*	`conf`	Using imprecise computing for improved non-preemptive real-time scheduling. DAC Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu
2017	—	`conf`	A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation. ISPA/IUCC Yanxiang Yang, Lijia Sun, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer
2017	—	`conf`	A comparative study on neural network-based prediction of smart community energy consumption. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI Lijia Sun, Jiang Hu, Yang Liu, Lin Liu, Shiyan Hu
2017	Misc	`conf`	A quantifiable approach to approximate computing: special session. CASES Chaofan Li, Deepashree Sengupta, Farhana Sharmin Snigdha, Wenbin Xu, Jiang Hu, Sachin S. Sapatnekar
2017	A	`conf`	A simple yet efficient accuracy configurable adder design. ISLPED Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu
2017	A	`conf`	Enhancing Datacenter Resource Management through Temporal Logic Constraints. IPDPS Hao He, Jiang Hu, Dilma Da Silva
2017	—	`conf`	Fast and Highly Scalable Bayesian MDP on a GPU Platform. BCB He Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu, Cliff C. N. Sze
2017	A	`conf`	Front-end-of-line attacks in split manufacturing. ICCAD Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	—	`conf`	Reinforcement Learning Control for Water-Efficient Agricultural Irrigation. ISPA/IUCC Lijia Sun, Yanxiang Yang, Jiang Hu, Dana Porter, Thomas H. Marek, Charles Hillyer
2017	—	`conf`	Routing perturbation for enhanced security in split manufacturing. ASP-DAC Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran
2017	A*	`conf`	SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. DAC Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar
2017	A	`conf`	Thwarting analog IC piracy via combinational locking. ITC Jiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu
2016	A	`conf`	Control synthesis and delay sensor deployment for efficient ASV designs. ICCAD Chaofan Li, Sachin S. Sapatnekar, Jiang Hu
2016	—	`conf`	GPU acceleration for Bayesian control of Markovian genetic regulatory networks. BHI He Zhou, Jiang Hu, Sunil P. Khatri, Frank Liu, Cliff C. N. Sze, Mohammadmahdi R. Yousefi
2016	A*	`conf`	Optimal design of JPEG hardware under the approximate computing paradigm. DAC Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar
2016	—	`conf`	Proximity Optimization for Adaptive Circuit Design. ISPD Ang Lu, Hao He, Jiang Hu
2016	J	`jnl`	Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Trans. Design Autom. Electr. Syst. Jae-Yeon Won, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu
2016	A*	`conf`	The cat and mouse in split manufacturing. DAC Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran
2015	C	`conf`	A pre-search assisted ILP approach to analog integrated circuit routing. ICCD Chia-Yu Wu, Helmut Graeb, Jiang Hu
2015	—	`conf`	Built-In Self Optimization for Variation Resilience of Analog Filters. ISVLSI Jiafan Wang, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu
2015	A	`conf`	Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits. ISLPED Hao He, Jiafan Wang, Jiang Hu
2015	C	`conf`	GPU acceleration for PCA-based statistical static timing analysis. ICCD Yiren Shen, Jiang Hu
2015	J	`jnl`	Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze
2015	A	`conf`	Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management. ISLPED Jae-Yeon Won, Paul Gratz, Srinivas Shakkottai, Jiang Hu
2015	A*	`conf`	Joint precision optimization and high level synthesis for approximate computing. DAC Chaofan Li, Wei Luo, Sachin S. Sapatnekar, Jiang Hu
2015	J	`jnl`	Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices. IEEE Trans. Ind. Electron. Jae-Yeon Won, Hyunsurk Ryu, Tobi Delbruck, Junhaeng Lee, Jiang Hu
2015	A	`conf`	Timing verification for adaptive integrated circuits. DATE Rohit Kumar, Bing Li, Yiren Shen, Ulf Schlichtmann, Jiang Hu
2014	A	`conf`	Algorithms for power-efficient QoS in application specific NoCs. ISLPED Hao He, Gongming Yang, Jiang Hu
2014	J	`jnl`	Regularity-constrained floorplanning for multi-core processors. Integr. Xi Chen, Jiang Hu, Ning Xu
2014	—	`conf`	STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip. NOCS Shalimar Rasheed, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu
2014	A*	`conf`	Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management. HPCA Jae-Yeon Won, Xi Chen, Paul Gratz, Jiang Hu, Vassos Soteriou
2013	J	`jnl`	Boostable Repeater Design for Variation Resilience in VLSI Interconnects. IEEE Trans. Very Large Scale Integr. Syst. Kyu-Nam Shim, Jiang Hu
2013	J	`jnl`	Dual-Level Adaptive Supply Voltage System for Variation Resilience. IEEE Trans. Very Large Scale Integr. Syst. Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
2013	A*	`conf`	Dynamic voltage and frequency scaling for shared resources in multicore processor designs. DAC Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras, Raid Zuhair Ayoub
2013	J	`jnl`	Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Cheng-Kok Koh
2013	J	`jnl`	In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Trans. Design Autom. Electr. Syst. Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras
2013	C	`conf`	Power gating with block migration in chip-multiprocessor last-level caches. ICCD David Kadjo, Hyungjun Kim, Paul Gratz, Jiang Hu, Raid Ayoub
2013	C	`conf`	Resource allocation algorithms for guaranteed service in application-specific NoCs. ICCD Gongming Yang, Hao He, Jiang Hu
2012	—	`conf`	A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience. DFT Kyu-Nam Shim, Jiang Hu
2012	J	`jnl`	Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
2012	J	`jnl`	Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Cheng-Kok Koh
2012	—	`conf`	In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. NOCS Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras
2012	—	`ed.`	International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012 ISPD Jiang Hu, Cheng-Kok Koh
2012	C	`conf`	Track assignment considering crosstalk-induced performance degradation. ICCD Qiong Zhao, Jiang Hu
2011	J	`jnl`	Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. VLSI Design Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu
2011	J	`jnl`	GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. Yifang Liu, Jiang Hu
2011	A	`conf`	Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu
2011	—	`conf`	Lagrangian relaxation for gate implementation selection. ISPD Yi-Le Huang, Jiang Hu, Weiping Shi
2011	—	`ed.`	Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 ISPD Yao-Wen Chang, Jiang Hu
2011	—	`conf`	Regularity-constrained floorplanning for multi-core processors. ISPD Xi Chen, Jiang Hu, Ning Xu
2011	J	`jnl`	Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yifang Liu, Rupesh S. Shelar, Jiang Hu
2010	J	`jnl`	A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yifang Liu, Jiang Hu
2010	—	`conf`	A dual-level adaptive supply voltage system for variation resilience. ISQED Kyu-Nam Shim, Jiang Hu, José Silva-Martínez
2010	—	`conf`	Accurate clock mesh sizing via sequential quadraticprogramming. ISPD Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li
2010	J	`jnl`	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2010	A	`conf`	Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD Yifang Liu, Yu Yang, Jiang Hu
2010	J	`jnl`	Combinatorial Algorithms for Fast Clock Mesh Optimization. IEEE Trans. Very Large Scale Integr. Syst. Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
2010	A*	`conf`	Detecting tangled logic structures in VLSI netlists. DAC Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn
2010	J	`jnl`	Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. IEEE Trans. Very Large Scale Integr. Syst. Rupak Samanta, Jiang Hu, Peng Li
2010	J	`jnl`	Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Trans. Very Large Scale Integr. Syst. Shiyan Hu, Patrik Shah, Jiang Hu
2010	—	`conf`	Physical design techniques for optimizing RTA-induced variations. ASP-DAC Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar
2010	A	`conf`	SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu
2010	J	`jnl`	Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2010	—	`conf`	Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu
2009	J	`jnl`	A fast general slew constrained minimum cost buffering algorithm. Microelectron. J. Shiyan Hu, Jiang Hu
2009	—	`conf`	A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD Yifang Liu, Jiang Hu
2009	J	`jnl`	A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2009	J	`jnl`	Clock Buffer Polarity Assignment for Power Noise Reduction. IEEE Trans. Very Large Scale Integr. Syst. Rupak Samanta, Ganesh Venkataraman, Jiang Hu
2009	J	`jnl`	Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. IEEE Trans. Very Large Scale Integr. Syst. Yang Liu, Tong Zhang, Jiang Hu
2009	A*	`conf`	GPU-based parallelization for fast circuit optimization. DAC Yifang Liu, Jiang Hu
2009	J	`jnl`	Gate Sizing for Cell-Library-Based Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyan Hu, Mahesh Ketkar, Jiang Hu
2009	—	`conf`	Impact of lithography-friendly circuit layout. ACM Great Lakes Symposium on VLSI Pratik J. Shah, Jiang Hu
2008	J	`jnl`	ASIC design flow considering lithography-induced effects. IET Circuits Devices Syst. Ke Cao, Jiang Hu
2008	—	`conf`	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu
2008	—	`conf`	Activity and register placement aware gated clock network design. ISPD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`ch.`	Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation Jiang Hu, Zhuo Li, Shiyan Hu
2008	J	`jnl`	Buffering Interconnect for Multicore Processor Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yifang Liu, Jiang Hu, Weiping Shi
2008	—	`ch.`	Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation Jiang Hu, Cliff C. N. Sze
2008	—	`conf`	Built-In Proactive Tuning System for Circuit Aging Resilience. DFT Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker
2008	—	`conf`	Discrete buffer and wire sizing for link-based non-tree clock networks. ISPD Rupak Samanta, Jiang Hu, Peng Li
2008	—	`conf`	Elastic Timing Scheme for Energy-Efficient and Robust Performance. ISQED Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu
2008	C	`conf`	Gate planning during placement for gated clock network. ICCD Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Handling partial correlations in yield prediction. ASP-DAC Sridhar Varadan, Janet Meiling Wang, Jiang Hu
2008	J	`jnl`	Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008	—	`conf`	Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian
2008	—	`conf`	Multi-scenario buffer insertion in multi-core processor designs. ISPD Yifang Liu, Jiang Hu, Weiping Shi
2008	J	`jnl`	Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2008	J	`jnl`	Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
2008	—	`ch.`	Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation Jiang Hu, Gabriel Robins, Cliff C. N. Sze
2008	J	`jnl`	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	—	`conf`	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman
2007	Misc	`conf`	A Placement Methodology for Robust Clocking. VLSI Design Ganesh Venkataraman, Jiang Hu
2007	—	`conf`	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2007	—	`conf`	An Efficient Algorithm for RLC Buffer Insertion. ISQED Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi
2007	J	`jnl`	An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
2007	A	`conf`	Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2007	J	`jnl`	Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze
2007	A*	`conf`	Gate Sizing For Cell Library-Based Designs. DAC Shiyan Hu, Mahesh Ketkar, Jiang Hu
2007	J	`jnl`	Integrated Placement and Skew Optimization for Rotary Clocking. IEEE Trans. Very Large Scale Integr. Syst. Ganesh Venkataraman, Jiang Hu, Frank Liu
2007	A	`conf`	Modeling, optimization and control of rotary traveling-wave oscillator. ICCAD Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen
2007	J	`jnl`	Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2007	—	`conf`	Pattern sensitive placement for manufacturability. ISPD Shiyan Hu, Jiang Hu
2007	—	`conf`	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
2007	—	`conf`	Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ISQED Yang Liu, Tong Zhang, Jiang Hu
2007	A	`conf`	Unified adaptivity optimization of clock and logic signals. ICCAD Shiyan Hu, Jiang Hu
2007	J	`jnl`	Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
2007	J	`jnl`	Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. Very Large Scale Integr. Syst. Ke Cao, Jiang Hu, Mosong Cheng
2006	A	`conf`	A new RLC buffer insertion algorithm. ICCAD Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
2006	J	`jnl`	Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2006	—	`conf`	An Improved AMG-based Method for Fast Power Grid Analysis. ISQED Cheng Zhuo, Jiang Hu, Kangsheng Chen
2006	—	`conf`	An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
2006	J	`jnl`	Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
2006	J	`jnl`	Antenna Avoidance in Layer Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Di Wu, Jiang Hu, Rabi N. Mahapatra
2006	A	`conf`	Associative skew clock routing for difficult instances. DATE Min-Seok Kim, Jiang Hu
2006	A	`conf`	Clock buffer polarity assignment for power noise reduction. ICCAD Rupak Samanta, Ganesh Venkataraman, Jiang Hu
2006	A	`conf`	Combinatorial algorithms for fast clock mesh optimization. ICCAD Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
2006	—	`conf`	Efficient Model Update for General Link-Insertion Networks. ISQED Zhuo Feng, Peng Li, Jiang Hu
2006	A*	`conf`	Fast algorithms for slew constrained minimum cost buffering. DAC Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
2006	A	`conf`	Fast decap allocation based on algebraic multigrid. ICCAD Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2006	C	`conf`	High performance clock routing in X-architecture. ISCAS Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
2006	A	`conf`	Integrated placement and skew optimization for rotary clocking. DATE Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
2006	—	`conf`	Low Power Trellis Decoder with Overscaled Supply Voltage. SiPS Yang Liu, Tong Zhang, Jiang Hu
2006	J	`jnl`	Reducing clock skew variability via crosslinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
2006	A*	`conf`	Standard cell characterization considering lithography induced variations. DAC Ke Cao, Sorin Dobre, Jiang Hu
2006	—	`conf`	Statistical clock tree routing for robustness to process variations. ISPD Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
2006	A*	`conf`	Steiner network construction for timing critical nets. DAC Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
2005	J	`jnl`	An efficient merging scheme for prescribed skew clock routing. IEEE Trans. Very Large Scale Integr. Syst. Rishi Chaturvedi, Jiang Hu
2005	—	`conf`	Clock network minimization methodology based on incremental placement. ASP-DAC Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
2005	—	`conf`	Coupling aware timing optimization and antenna avoidance in layer assignment. ISPD Di Wu, Jiang Hu, Rabi N. Mahapatra
2005	A	`conf`	DiCER: distributed and cost-effective redundancy for variation tolerance. ICCAD Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra
2005	—	`conf`	Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD Anand Rajaram, David Z. Pan, Jiang Hu
2005	—	`conf`	Library cell layout with Alt-PSM compliance and composability. ASP-DAC Ke Cao, Puneet Dhawan, Jiang Hu
2005	—	`conf`	Making fast buffer insertion even faster via approximation techniques. ASP-DAC Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	J	`jnl`	Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Navigating registers in placement for clock network minimization. DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	A*	`conf`	Path based buffer insertion. DAC Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
2005	A	`conf`	Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
2005	—	`conf`	Register placement for low power clock network. ASP-DAC Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
2005	—	`conf`	Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
2005	—	`conf`	Timing driven track routing considering coupling capacitance. ASP-DAC Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
2004	J	`jnl`	A methodology for the simultaneous design of supply and signal networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2004	—	`conf`	A place and route aware buffered Steiner tree construction. ASP-DAC Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
2004	A	`conf`	Accurate estimation of global buffer delay within a floorplan. ICCAD Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
2004	A	`conf`	Exploiting level sensitive latches in wire pipelining. ICCAD V. Seth, Min Zhao, Jiang Hu
2004	A*	`conf`	Fast and flexible buffer trees that navigate the physical layout environment. DAC Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
2004	—	`conf`	Layer assignment for crosstalk risk minimization. ASP-DAC Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
2004	J	`jnl`	Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
2004	A*	`conf`	Reducing clock skew variability via cross links. DAC Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
2004	J	`jnl`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2003	C	`conf`	A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ICCD Rishi Chaturvedi, Jiang Hu
2003	J	`jnl`	A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2003	A	`conf`	Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
2003	J	`jnl`	Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
2003	—	`conf`	Porosity aware buffered steiner tree construction. ISPD Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
2003	—	`conf`	Process variation aware clock tree routing. ISPD Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
2002	J	`jnl`	A timing-constrained simultaneous global routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Sachin S. Sapatnekar
2002	—	`conf`	Buffer insertion with adaptive blockage avoidance. ISPD Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
2002	A*	`conf`	Congestion-driven codesign of power and signal networks. DAC Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2002	J	`jnl`	Performance Driven Global Routing Through Gradual Refinement. VLSI Design Jiang Hu, Sachin S. Sapatnekar
2002	—	`conf`	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
2001	A*	`conf`	A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
2001	J	`jnl`	A survey on multi-net global routing for integrated circuits. Integr. Jiang Hu, Sachin S. Sapatnekar
2001	—	`conf`	Buffered Steiner trees for difficult instances. ISPD Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
2001	C	`conf`	Performance Driven Global Routing Through Gradual Refinement. ICCD Jiang Hu, Sachin S. Sapatnekar
2001	J	`jnl`	Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2001	—	`conf`	Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
2000	A	`conf`	A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD Jiang Hu, Sachin S. Sapatnekar
2000	J	`jnl`	Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiang Hu, Sachin S. Sapatnekar
1999	A*	`conf`	FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC Jiang Hu, Sachin S. Sapatnekar
1999	J	`jnl`	Non-Hanan routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
1999	—	`conf`	Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD Jiang Hu, Sachin S. Sapatnekar