Jiang Chau Wang

39 papers B 2C 1Misc 1Journal 8Unranked 27

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	The functional verification of a satellite transponder. LASCAS Vinicius Martins, Jerson Paulo Guex, Luciana Shiroma Montali, Jiang Chau Wang
2017	—	`conf`	Mixed signal verification to avoid integration mismatch in complex SoCs. LATS Vinicius Martins, Jiang Chau Wang, Jerson Paulo Guex
2017	—	`conf`	Multifractal on-chip traffic generation under TLM. SoCC Jose Eduardo Chiarelli Bueno Filho, Jiang Chau Wang
2016	—	`conf`	Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. SoCC Jose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Jiang Chau Wang
2016	—	`conf`	Scenario-Aware Workload Characterization Based on a Max-Plus Linear Representation. FORMATS Gustavo A. Patiño-Álvarez, Jiang Chau Wang
2015	J	`jnl`	A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. J. Electron. Test. Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2015	—	`conf`	DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost. ARC Ernesto Villegas Castillo, Gabriele Miorandi, Davide Bertozzi, Jiang Chau Wang
2015	—	`conf`	Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost. LASCAS Ernesto Villegas Castillo, Jiang Chau Wang, Gabriele Miorandi, Davide Bertozzi
2015	—	`conf`	Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
2015	J	`jnl`	Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Int. J. Reconfigurable Comput. Jonas Gomes Filho, Marius Strum, Jiang Chau Wang
2014	—	`conf`	A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. LATW Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2014	—	`conf`	DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm. NOCS Ernesto Villegas Castillo, Gabriele Miorandi, Jiang Chau Wang
2013	—	`conf`	3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. GECCO (Companion) Martha Johanna Sepúlveda, Guy Gogniat, Daniel Mauricio Sepúlveda, Ricardo Pires, Jiang Chau Wang, Marius Strum
2013	—	`conf`	An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2013	—	`conf`	Exploring the problems of placement and mapping in NoC-based reconfizurable systems. ReConFig Jonas Gomes Filho, Jiang Chau Wang
2013	—	`conf`	Formal equivalence checking between high-level and RTL hardware designs. LATW Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2013	—	`conf`	Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. IDT Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2013	J	`jnl`	Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electron. Test. Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
2013	—	`conf`	PrOCov: Probabilistic output coverage model. LATW Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang
2013	—	`conf`	Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) Martha Johanna Sepúlveda, Jiang Chau Wang, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires
2012	J	`jnl`	QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfigurable Comput. Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Workload and task characterization based on operation modes timing analysis. SoCC Gustavo A. Patiño-Álvarez, Jorge González, Jiang Chau Wang, Marius Strum
2011	J	`jnl`	A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electron. Test. Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
2011	—	`conf`	Dynamic NoC-based architecture for MPSoC security implementation. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2010	J	`jnl`	Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Trans. Comput. Sci. Johanna Sepúlveda, Ricardo Pires, Marius Strum, Jiang Chau Wang
2010	—	`conf`	The LRD traffic impact on the NoC-based SoCs. SBCCI Johanna Sepúlveda, Marius Strum, Jiang Chau Wang, Ricardo Pires
2009	—	`conf`	A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2009	B	`conf`	The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang, Jose Artur Quilici González
2007	—	`conf`	A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI Frederico De Faria, Marius Strum, Jiang Chau Wang
2005	B	`conf`	A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
2005	Misc	`conf`	Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
2005	—	`conf`	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
2004	J	`jnl`	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electron. Test. Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires
2003	J	`jnl`	Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang, Wagner Chiepa Cunha
1999	—	`conf`	Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
1998	—	`conf`	A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang
1995	C	`conf`	Collective Test Generation and Test Set Compaction. ISCAS Jiang Chau Wang, Edward P. Stabler