Jianfei Jiang

85 papers A* 7A 5B 3C 10Journal 35Unranked 25
YearRankTypeTitle / Venue / Authors
2026 J jnl
A power-efficient multiplier with fine-grained power management.
Microelectron. J.
Tong Li, Honglan Jiang, Qin Wang, Jianfei Jiang, Zhigang Mao
2026 J jnl
DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation.
CoRR
Yiwei Wu, Yifan Wu, Yunhao Xiong, Dengwei Zhao, Jiaxuan Shen, Jianfei Jiang, Guanghui He, Shikui Tu, Yanan Sun
2026 J jnl
LUT-ALMs: Trading Off Accuracy and Power for Approximate Logarithmic Multipliers via LUT Optimization.
IEEE Trans. Computers
Wenhui Zhang, Xinkuang Geng, Xiaolu Hu, Hui Wang, Jianfei Jiang, Qin Wang, Siting Liu, Jie Han, Honglan Jiang
2026 J jnl
Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked SRAM Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pengyu Liu, Liyan Chen, Zelong Yuan, Yingkun Liu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2026 J jnl
Signal integrity-aware multi-path design workflow for ultra-large-scale three-dimensional chips: A logic-on-memory stacking case study.
Microelectron. J.
Ang Li, Jianfei Jiang, Naifeng Jing, Yanan Sun, Zhigang Mao, Qin Wang
2026 — conf
Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption.
ASP-DAC
Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025 J jnl
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2025 J jnl
An Energy-Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2.
IEEE Trans. Circuits Syst. II Express Briefs
Jialei Sun, Lingyi Liu, Kunyue Li, Shuaipeng Li, Sai Gao, Zizheng Dong, Jianfei Jiang, Fangzhen Wu
2025 A* conf
AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing.
HPCA
Liyan Chen, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 A* conf
AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-Memory.
DAC
Liyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 A* conf
BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern Pruning.
DAC
Gang Wang, Siqi Cai, Zhenyu Li, Wenjie Li, Dongxu Lyu, Yanan Sun, Jianfei Jiang, Guanghui He
2025 J jnl
Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Liyan Chen, Pengyu Liu, Dongxu Lyu, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 J jnl
Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kunyue Li, Shuaipeng Li, Xiaoyan Li, Zizheng Dong, Sai Gao, Jialei Sun, Naifeng Jing, Qin Wang, Guanghui He, Jianfei Jiang
2025 J jnl
Efficient Extraction and Packing Modules for Posit Multipliers.
IEEE Trans. Circuits Syst. II Express Briefs
Tong Li, Honglan Jiang, Zhou Wang, Qin Wang, Jianfei Jiang, Zhigang Mao
2025 A conf
HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler.
DATE
Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025 J jnl
IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Jinming Zhang, Zhihong Chen, Yaoyao Ye, Hao Chen, Xiao Han, Jianfei Jiang, Weiguang Sheng, Ningyi Xu, Yong Lian, Guanghui He
2025 A* conf
KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM Inference.
DAC
Zhenyu Li, Dongxu Lyu, Gang Wang, Yuzhou Chen, Liyan Chen, Wenjie Li, Jianfei Jiang, Yanan Sun, Guanghui He
2025 J jnl
MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Honglan Jiang, Zhigang Mao, Qin Wang
2025 — conf
MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing.
ASP-DAC
Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2025 A* conf
Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator.
DAC
Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing
2025 C conf
RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V.
ICCD
Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing, Qin Wang
2025 A* conf
VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator.
DAC
Zhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang, Zhenyu Li, Jianfei Jiang, Yanan Sun, Guanghui He
2025 J jnl
VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible Accelerator.
CoRR
Zhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang, Zhenyu Li, Jianfei Jiang, Yanan Sun, Guanghui He
2024 J jnl
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zhang, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 C conf
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.
ISCAS
Lin Xie, Zizheng Dong, Jialei Sun, Sai Gao, Shuaipeng Li, Naifeng Jing, Qin Wang, Jianfei Jiang
2024 J jnl
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pengyu Liu, Ang Li, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 J jnl
A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.
Expert Syst. Appl.
Kunyue Li, Zhengji Zhao, Qixuan Cai, Qin Wang, Naifeng Jing, Zhigang Mao, Jianfei Jiang
2024 B conf
Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.
ASPDAC
Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 A conf
Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks.
DATE
Xinkuang Geng, Siting Liu, Jianfei Jiang, Kai Jiang, Honglan Jiang
2024 J jnl
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 A* conf
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators.
DAC
Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing
2024 J jnl
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2024 B conf
SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.
ASPDAC
Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2024 — conf
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.
ACM Great Lakes Symposium on VLSI
Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang
2023 — conf
A Hierarchical Communication Algorithm for Distributed Deep Learning Training.
MWSCAS
Jiayu Zhang, Shaojun Cheng, Feng Dong, Ke Chen, Yong Qiao, Zhigang Mao, Jianfei Jiang
2023 J jnl
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Yin, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao
2023 C conf
ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.
ICCD
Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang
2023 — conf
An Efficient near-Bank Processing Architecture for Personalized Recommendation System.
ASP-DAC
Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
2023 — conf
An NoC-based CNN Accelerator for Edge Computing.
ASICON
Jianing Gao, Qiming Shao, Fangyu Deng, Qin Wang, Naifeng Jing, Jianfei Jiang
2023 J jnl
Exploiting bit sparsity in both activation and weight in neural networks accelerators.
Integr.
Naifeng Jing, Zihan Zhang, Yongshuai Sun, Pengyu Liu, Liyan Chen, Qin Wang, Jianfei Jiang
2023 — conf
High-Performance Genomic Analysis Heterogeneous System Using OpenCL.
ASICON
Jianing Gao, Lingyi Liu, Qin Wang, Naifeng Jing, Jianfei Jiang
2023 — conf
MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5.
ASICON
Xiaoyan Li, Zizheng Dong, Shuaipeng Li, Sai Gao, Jianfei Jiang, Guanghui He, Zhigang Mao
2023 B conf
Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.
FPL
Pengyu Liu, Zihan Zhang, Chen Yin, Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing
2023 — conf
RTMDet-R2: An Improved Real-Time Rotated Object Detector.
PRCV (12)
Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
2023 — conf
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.
ASICON
Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing
2022 J jnl
A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network.
IEEE Trans. Circuits Syst. II Express Briefs
Jianfei Jiang, Mingjun Jiang, Jiayu Zhang, Feng Dong
2022 J jnl
A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett.
Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
2022 J jnl
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.
ACM Trans. Design Autom. Electr. Syst.
Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen
2022 J jnl
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zihan Zhang, Jianfei Jiang, Yongxin Zhu, Qin Wang, Zhigang Mao, Naifeng Jing
2022 J jnl
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
2022 — conf
Boosting ReRAM-based DNN by Row Activation Oversubscription.
ASP-DAC
Mengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing
2021 — conf
A CPU-FPGA Based Heterogeneous Accelerator for RepVGG.
ASICON
Yiliang Guo, Mingjun Jiang, Feng Dong, Kehua Yu, Ke Chen, Wei Qu, Jianfei Jiang
2021 — conf
A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.
BigDataSecurity
Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
2021 C conf
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator.
ISCAS
Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing
2021 A conf
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.
DATE
Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
2021 A conf
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.
DATE
Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
2020 J jnl
An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture.
IEEE Trans. Circuits Syst.
Jiaming Tu, Mengdan Lou, Jianfei Jiang, Dewu Shu, Guanghui He
2020 C conf
Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.
ISCAS
Tu Hong, Ning Guan, Chen Yin, Qin Wang, Jianfei Jiang, Jing Jin, Guanghui He, Naifeng Jing
2020 — conf
Frequency Attention Network: Blind Noise Removal for Real Images.
ACCV (2)
Hongcheng Mo, Jianfei Jiang, Qin Wang, Dong Yin, Pengyu Dong, Jingjun Tian
2020 J jnl
Priority Branches for Ship Detection in Optical Remote Sensing Images.
Remote. Sens.
Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
2019 — conf
A New Approximate Multiplier Design for Digital Signal Processing.
ASICON
Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang
2019 J jnl
A New Cellular-Based Redundant TSV Structure for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst.
Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng
2019 J jnl
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.
ACM Trans. Design Autom. Electr. Syst.
Taozhong Li, Qin Wang, Yongxin Zhu, Jianfei Jiang, Guanghui He, Jing Jin, Zhigang Mao, Naifeng Jing
2019 C conf
A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.
ISCAS
Sijie Zheng, Hongjun You, Guanghui He, Qin Wang, Tao Si, Jianfei Jiang, Jing Jin, Naifeng Jing
2019 — conf
Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture.
ASICON
Junning Jiang, Liang Cai, Feng Dong, Kehua Yu, Ke Chen, Wei Qu, Jianfei Jiang
2017 C conf
A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency.
ISCAS
Xuwei Jin, Wei Jin, Hao Zhang, Jianfei Jiang, Weifeng He
2017 J jnl
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.
Integr.
Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing
2017 — conf
A metastability-based true random number generator on FPGA.
ASICON
Chaoyang Li, Qin Wang, Jianfei Jiang, Nin Guan
2017 — conf
An on-chip circuit for timing measurement of SRAM IP.
ASICON
Xianjie Long, Qin Wang, Jianfei Jiang, Nin Guan
2017 J jnl
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.
Integr.
Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao
2016 J jnl
Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.
J. Circuits Syst. Comput.
Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
2016 J jnl
Parallel SER analysis for combinational and sequential standard cell circuits.
Microelectron. J.
Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2015 — conf
A contactless testing methodology for pre-bond interposer.
MWSCAS
Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
2015 — conf
A crosstalk avoidance scheme based on re-layout of signal TSV.
ASICON
Jiayi Hu, Qin Wang, Jianfei Jiang, Jing Xie, Zhigang Mao
2015 J jnl
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao
2015 J jnl
Design optimization for capacitive-resistively driven on-chip global interconnect.
IEICE Electron. Express
Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
2015 A conf
Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.
ICCAD
Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao
2013 — conf
Design of a high voltage stimulator chip for a stroke rehabilitation system.
EMBC
Lei Zeng, Xin Yi, Sheng Lu, Yuan Lou, Jianfei Jiang, Hongen Qu, Ning Lan, Guoxing Wang
2013 C conf
Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.
ISCAS
Zhenyang Chen, Qin Wang, Jing Xie, Jin Tian, Jianfei Jiang, Yufei Li, Wen Yin
2012 C conf
A pre-emphasis circuit design for high speed on-chip global interconnect.
ISCAS
Jianfei Jiang, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He
2012 — conf
Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.
IPDPS Workshops
Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao
2011 C conf
A clock-less transceiver for global interconnect.
VLSI-SoC
Jianfei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao
2011 — conf
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.
ASICON
Can Wang, Qin Wang, Jianfei Jiang
2011 — conf
A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.
ICECS
Xu Wang, Jianfei Jiang, Zhi-Gang Mao, Bingjing Ge, Xinglong Zhao
2011 — conf
An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.
ASICON
Zaixiao Zheng, Zhigang Mao, Jianfei Jiang