Jianan Mu

37 papers A* 6A 6B 1Misc 1Journal 16Unranked 7
YearRankTypeTitle / Venue / Authors
2026 — conf
FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption.
ASP-DAC
Shangyi Shi, Husheng Han, Jianan Mu, Xinyao Zheng, Ling Liang, Hang Lu, Zidong Du, Xiaowei Li, Xing Hu
2026 J jnl
On the Vulnerability of FHE Computation to Silent Data Corruption.
CoRR
Jianan Mu, Ge Yu, Zhaoxuan Kan, Song Bian, Liang Kong, Zizhen Liu, Cheng Liu, Jing Ye, Huawei Li
2026 J jnl
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction.
CoRR
Jiaping Tang, Jianan Mu, TianYun Ma, Zhiteng Chao, Jing Ye, Huawei Li
2026 J jnl
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning.
CoRR
Xinyu Zhang, Zhiteng Chao, Yonghao Wang, Bin Sun, TianYun Ma, Tianmeng Yang, Jianan Mu, Jing Justin Ye, Huawei Li
2025 A* conf
Bridging Layout and RTL: Knowledge Distillation based Timing Prediction.
ICML
Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Justin Ye, Bei Yu, Huawei Li
2025 J jnl
CodeV-R1: Reasoning-Enhanced Verilog Generation.
CoRR
Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
2025 A* conf
EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components.
DAC
Mingjun Wang, Hui Wang, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025 A conf
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.
DATE
Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025 J jnl
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.
CoRR
Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shenwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2025 — conf
ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring.
ASP-DAC
Mingjun Wang, Hui Wang, Zizhen Liu, Feng Gu, Jianan Mu, Jiaping Tang, Jun Gao, Huawei Li, Jing Ye, Xiaowei Li
2025 J jnl
Extend IVerilog to Support Batch RTL Fault Simulation.
CoRR
Jiaping Tang, Jianan Mu, Zizhen Liu, Zhiteng Chao, Jing Ye, Huawei Li
2025 J jnl
Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware.
CoRR
Jianan Mu, Mingyu Shi, Yining Wang, Tianmeng Yang, Bin Sun, Xing Hu, Jing Ye, Huawei Li
2025 A* conf
FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks.
ICML
Zhaoxuan Kan, Husheng Han, Shangyi Shi, Tenghui Hua, Hang Lu, Xiaowei Li, Jianan Mu, Xing Hu
2025 J jnl
FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks.
CoRR
Zhaoxuan Kan, Husheng Han, Shangyi Shi, Tenghui Hua, Hang Lu, Xiaowei Li, Jianan Mu, Xing Hu
2025 J jnl
FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption.
CoRR
Shangyi Shi, Husheng Han, Jianan Mu, Xinyao Zheng, Ling Liang, Hang Lu, Zidong Du, Xiaowei Li, Xing Hu, Qi Guo
2025 Misc conf
HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion.
VTS
Zhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye, Xiaowei Li, Huawei Li
2025 J jnl
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning.
CoRR
Bin Sun, Rengang Zhang, Zhiteng Chao, Zizhen Liu, Jianan Mu, Jing Ye, Huawei Li
2025 J jnl
Large Processor Chip Model.
CoRR
Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuanjing Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaochun Ye, Kuai Yu, Rui Zhang, Shuoming Zhang, Jiacheng Zhao
2025 A* conf
MOSS: Multi-Modal Representation Learning on Sequential Circuits.
DAC
Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, Huawei Li
2025 J jnl
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction.
CoRR
Bin Sun, Jingyi Zhou, Jianan Mu, Zhiteng Chao, Tianmeng Yang, Ziyue Xu, Jing Ye, Huawei Li
2025 A* conf
PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT.
DAC
Zhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai, Jing Ye, Xiaowei Li, Huawei Li
2025 A conf
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule.
ICCAD
Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025 J jnl
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule.
CoRR
Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li
2025 A conf
TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration.
ITC
Zhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye, Xiaowei Li, Huawei Li
2025 J jnl
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT.
CoRR
Zhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu, Rui Zhang, Jing Ye, Huawei Li
2025 A conf
VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning.
ICCAD
Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, Bei Yu
2024 — conf
Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction.
ATS
Jiaping Tang, Zizhen Liu, Jianan Mu, Feng Gu, Mingjun Wang, Wenxing Li, Jing Ye, Xiaowei Li, Huawei Li
2024 A* conf
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.
DAC
Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li
2024 A conf
DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism.
ICCAD
Feng Gu, Mingjun Wang, Jianan Mu, Zizhen Liu, Jiaping Tang, Hui Wang, Yonghao Wang, Jing Ye, Huawei Li, Xiaowei Li
2024 — conf
Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.
ITC-Asia
Mingjun Wang, Hui Wang, Jianan Mu, Zizhen Liu, Jun Gao, Jing Ye, Huawei Li, Xiaowei Li
2024 — conf
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing.
ASPLOS (4)
Husheng Han, Xinyao Zheng, Yuanbo Wen, Yifan Hao, Erhu Feng, Ling Liang, Jianan Mu, Xiaqing Li, TianYun Ma, Pengwei Jin, Xinkai Song, Zidong Du, Qi Guo, Xing Hu
2024 J jnl
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing.
CoRR
Husheng Han, Xinyao Zheng, Yuanbo Wen, Yifan Hao, Erhu Feng, Ling Liang, Jianan Mu, Xiaqing Li, TianYun Ma, Pengwei Jin, Xinkai Song, Zidong Du, Qi Guo, Xing Hu
2023 — conf
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
ATS
Jianan Mu, Huajie Tan, Shuai Chen, Min Cai, Jing Ye, Huawei Li, Xiaowei Li
2023 A conf
Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.
DATE
Jianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li
2023 B conf
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.
ETS
Chaofang Ma, Jianan Mu, Jing Ye, Shuai Chen, Yuan Cao, Huawei Li, Xiaowei Li
2023 J jnl
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
2022 — conf
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.
ASP-DAC
Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao