Jian Zhang

15 papers Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
A 14GHz Chopper-Refolding Sampling PLL Achieving 33.8$\text{fs}_{\text{rms}}$ and 80.8dBc Reference Spur with a kT/C-Noise-Cancellation SPD.
ISSCC
Yichen Liu, Jian Zhang, Xiaosen Liu, Yan Wang
2025 J jnl
A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Jian Zhang, Ming Zhai, Yichen Liu, Xiangjie Yi, Dawei Wang, Wei Zhu, Yan Wang
2024 — conf
32.8 A 27.8-to-38.7GHz Load-Modulated Balanced Power Amplifier with Scalable 7-to-1 Load-Modulated Power-Combine Network Achieving 27.2dBm Output Power and 28.8%/23.2%/16.3%/11.9% Peak/6/9/12dB Back-Off Efficiency.
ISSCC
Wei Zhu, Jiazhi Ying, Long Chen, Jian Zhang, Guanshen Lv, Xiangjie Yi, Zhiqiang Zhao, Zunxiang Wang, Yan Wang, Wenhua Chen, Houjun Sun
2024 J jnl
Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sen Yin, Ruitao Wang, Jian Zhang, Xiaosen Liu, Yan Wang
2023 — conf
A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS Technology.
A-SSCC
Wei Zhu, Jian Zhang, Jiazhi Ying, Xiangjie Yi, Yan Wang, Houjun Sun
2023 — conf
A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dB.
A-SSCC
Jian Zhang, Wei Zhu, Dawei Wang, Xiangjie Yi, Ruitao Wang, Yan Wang
2023 J jnl
Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sen Yin, Ruitao Wang, Jian Zhang, Xiaosen Liu, Yan Wang
2022 — conf
A 1V 32.1 dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process.
ISSCC
Wei Zhu, Jiawen Wang, Ruitao Wang, Jian Zhang, Chenguang Li, Sen Yin, Yan Wang
2022 — conf
A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP.
VLSI Technology and Circuits
Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang
2022 — conf
An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental Learning.
ASP-DAC
Sen Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang
2022 — conf
An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology.
VLSI Technology and Circuits
Wei Zhu, Ruitao Wang, Jian Zhang, Jiawen Wang, Chenguang Li, Yan Wang
2022 J jnl
Asynchronous Parallel Expected Improvement Matrix-Based Constrained Multi-Objective Optimization for Analog Circuit Sizing.
IEEE Trans. Circuits Syst. II Express Briefs
Sen Yin, Ruitao Wang, Jian Zhang, Yan Wang
2022 — conf
Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique.
ISQED
Zhikai Wang, Wenfei Hu, Jingbo Zhou, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Dejing Dou, Zuochang Ye, Yan Wang
2021 — conf
An efficient optimization method of RF passive components using RBF model.
ASICON
Sen Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang
2021 — conf
Large-scale Integrated Circuits Simulation Based on CNT-FET Model.
ICICDT
Zhikai Wang, Wenfei Hu, Ziyu Gu, Wenyuan Zhang, Sen Yin, Ruitao Wang, Jian Zhang, Yan Wang