Jian Wang

28 papers A* 7B 2C 2Misc 3Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
Using machine learning techniques for DSP software performance prediction at source code level.
Connect. Sci.
Weihua Liu, Erh-Wen Hu, Bogong Su, Jian Wang
2019 J jnl
Comparing DSP Software Performance Prediction Models at Source Code Level - From Analytical to Statistical.
J. Softw.
Erh-Wen Hu, Weihua Liu, Bogong Su, Jian Wang
2017 C conf
Software performance prediction at source level.
SERA
Erh-Wen Hu, Bogong Su, Jian Wang
2006 — conf
New DSP Benchmark based on Selectable Mode Vocoder (SMV).
CDES
Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang
2004 — conf
Loop optimization with tradeoff between cycle count and code size for DSP applications.
EUSIPCO
Bogong Su, Jian Wang, Rafi Rabipour, Erh-Wen Hu, Joseph B. Manzano
2004 C conf
Software De-Pipelining Technique.
SCAM
Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano
2003 — conf
De-pipeline a software-pipelined loop.
ICASSP (2)
Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano
2000 Misc conf
A scalable loop optimization approach for scalable DSP processors.
ICASSP
Jian Wang, Bogong Su, Erh-Wen Hu
1999 Misc conf
Source-level loop optimization for DSP code generation.
ICASSP
Bogong Su, Jian Wang, Andrew Esguerra
1998 Misc conf
Software pipelining of nested loops for real-time DSP applications.
ICASSP
Jian Wang, Bogong Su
1997 — conf
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.
IEEE PACT
Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao
1996 B conf
Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.
CC
Jian Wang, Guang R. Gao
1995 B conf
Decomposed software pipelining with reduced register requirement.
PACT
Jian Wang, Andreas Krall, M. Anton Ertl
1995 J jnl
Trace software pipelining.
J. Comput. Sci. Technol.
Jian Wang, Andreas Krall, M. Anton Ertl
1994 A* conf
A study of pointer aliasing for software pipelining using run-time disambiguation.
MICRO
Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu
1994 J jnl
Decomposed software pipelining: A new perspective and a new approach.
Int. J. Parallel Program.
Jian Wang, Christine Eisenbeis, Martin Jourdan, Bogong Su
1994 A* conf
Software pipelining with register allocation and spilling.
MICRO
Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis
1994 — conf
Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches.
IFIP PACT
Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis
1994 J jnl
Using timed Petri net to model instruction-level loop scheduling with resource constraints.
J. Comput. Sci. Technol.
Jian Wang, Christine Eisenbeis, Bogong Su
1993 — conf
Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs.
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Jian Wang, Christine Eisenbeis
1993 J jnl
URPR-1: A single-chip VLIW architecture.
Microprocess. Microprogramming
Bogong Su, Jian Wang, Zhizhong Tang, Chihong Zhang, Wei Zhao
1992 J jnl
Foresighted Instruction Scheduling Under Timing Constraints.
IEEE Trans. Computers
Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang
1991 A* conf
GURPR
MICRO
Bogong Su, Jian Wang
1990 A* conf
A software pipelining based VLIW architecture and optimizing compiler.
MICRO
Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu
1988 A* conf
Global microcode compaction under timing constraints.
MICRO
Bogong Su, Jian Wang, Jinshi Xia
1988 — conf
The Architecture of a Distributed Knowledge Base System.
DS-3
Bogong Su, Chunyi Shi, Kehong Wang, Peng Hu, Hao Shi, Jian Wang
1987 A* conf
GURPR - a method for global software pipelining.
MICRO
Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia
1987 A* conf
Microcode compaction with timing constraints.
MICRO
Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia