Jian-Hsing Lee

23 papers Unranked 23

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power. ICCE-Taiwan Yeh-Jen Huang, Li-Yang Hong, Yeh-Ning Jou, Jian-Hsing Lee
2024	—	`conf`	The Influence of the Block Design on the ID-VD Curves of Power Transistor for E-SOA Characterization. ICCE-Taiwan Chun-Chih Chen, Shih-Chieh Chien, Chien-Wei Wang, Yu-Sheng Chiu, Jung-Tsun Chuang, Li-Fan Chen, Chieh-Yao Chuang, Jian-Hsing Lee
2023	—	`conf`	A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor. IRPS Jian-Hsing Lee, Gong-Kai Lin, Chun-Chih Chen, Li-Fan Chen, Chien-Wei Wang, Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Ke-Horng Chen
2023	—	`conf`	Bipolar Transistors' Holding Phenomena. ICCE-Taiwan Shao-Chang Huang, Kai-Chieh Hsu, Chih-Hsuan Lin, Chien-Wei Wang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen
2023	—	`conf`	Optimizing Device Metal Routing Layouts by the Simulation Tool. ICCE-Taiwan Shao-Chang Huang, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Chien-Wei Wang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Kuan-I Ho, Che-Hua Chang, Hsiao-Ying Yang, Chung-Ren Lao, Jian-Hsing Lee, Ke-Horng Chen
2023	—	`conf`	Transmission Line Pulse Width Impacting on Device Performances. ICCE-Taiwan Shao-Chang Huang, Chien-Wei Wang, Chih-Hsuan Lin, Kai-Chieh Hsu, Ching-Ho Li, Chih-Cherng Liao, Jung-Tsun Chuang, Gong-Kai Lin, Lin-Fan Chen, Chun-Chih Chen, Yeh-Ning Jou, Jian-Hsing Lee, Ke-Horng Chen
2022	—	`conf`	EOS Endurance Power Circuits without Depletion Mode Devices. ICCE-TW Shao-Chang Huang, Jian-Hsing Lee, Ching-Ho Li, Sue-Yi Chen, Chih-Hsuan Lin, Chun-Chih Chen, Li-Fan Chen, Gong-Kai Lin, Chien-Wei Wang, Kai-Chieh Hsu, Szu-Chi Chen, Shang-Chuan Pai, Fu-Wei Pai, Yin-Wei Peng, Chih-Cherng Liao, Ke-Horng Chen
2022	—	`conf`	Gate Voltages Impacting on Latch-up Measurements. ICCE-TW Shao-Chang Huang, Jian-Hsing Lee, Chun-Chih Chen, Ching-Ho Li, Chih-Cherng Liao, Kai-Chieh Hsu, Gong-Kai Lin, Li-Fan Chen, Chien-Wei Wang, Chih-Hsuan Lin, Yeh-Ning Jou, Ke-Horng Chen
2022	—	`conf`	Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection. IRPS Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Li-Fan Chen, Yeh-Ning Jou, Shin-Cheng Lin, Walter Wohlmuth, Chih-Cherng Liao, Ching-Ho Li, Shoa-Chang Huang, Ke-Horng Chen
2021	—	`conf`	Optimizing Power IC Layouts by Simulation Tools. ICCE-TW Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee
2021	—	`conf`	Signal Control Switching Applied on Large Array Devices' Layouts. ICCE-TW Shao-Chang Huang, Yu-Yung Kao, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Ke-Horng Chen
2021	—	`conf`	Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process. IRPS Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker
2020	—	`conf`	Signal Control Switching for Improving Large Array Devices' ESD Performances. ICCE-TW Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Chih-Hsuan Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen
2020	—	`conf`	The Correlations between ESD and TLP in Large Array Devices. ICCE-TW Shao-Chang Huang, Ching-Ho Li, Li-Fan Chen, Chun-Chih Chen, Ting-You Lin, Kai-Chieh Hsu, Gong-Kai Lin, Jian-Hsing Lee, Yu-Yung Kao, Ke-Horng Chen
2019	—	`conf`	Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. ICCE-TW Shao-Chang Huang, Chih-Cherng Liao, Hsien-Feng Liao, Shou-Peng Weng, Karuna Nidhi, Yu-Kai Wang, Yi-Jen Chen, Hwa-Chyi Chiou, Yeh-Ning Jou, Jian-Hsing Lee
2019	—	`conf`	Physical Model for ESD Human Body Model to Transmission Line Pulse. IRPS Jian-Hsing Lee, Natarajan Mahadeva Iyer, Timothy J. Maloney
2019	—	`conf`	Tunable Holding-Voltage High Voltage ESD Devices. IRPS Jian-Hsing Lee, Natarajan Mahadeva Iyer
2015	—	`conf`	Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate. IRPS Tzu-Cheng Kao, Jian-Hsing Lee, Chen-Hsin Lien, Chih-Hsien Wang, Kuang-Cheng Tai, Hung-Der Su
2015	—	`conf`	Methodology to achieve planar technology-like ESD performance in FINFET process. IRPS Jian-Hsing Lee, Manjunatha Prabhu, Konstantin Korablev, Jagar Singh, Mahadeva Iyer Natarajan, Shesh Mani Pandey
2015	—	`conf`	Printed-circuit board (PCB) charge induced product yield-loss during the final test. IRPS Jian-Hsing Lee, Kunihiko Takahashi, Manjunatha Prabhu, Mahadeva Iyer Natarajan
2015	—	`conf`	Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering. IRPS Tzu-Cheng Kao, Chen-Hsin Lien, Chien-Wei Chiu, Jian-Hsing Lee, Yen-Hsiang Lo, Chung-Yu Hung, Tsung-Yi Huang, Hung-Der Su
2005	—	`conf`	A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. ISCAS (2) Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong
2002	—	`conf`	The embedded SCR NMOS and low capacitance ESD protection device. CICC Jian-Hsing Lee, Yi-Hsun Wu, K. R. Peng, R. Y. Chang, Talee Yu, Tong-Chern Ong