Jiajia Li

25 papers A* 2A 5Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2020 J jnl
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kwangsoo Han, Andrew B. Kahng, Jiajia Li
2019 J jnl
Enhancing sensitivity-based power reduction for an industry IC design context.
Integr.
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
2018 J jnl
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sorin Dobre, Andrew B. Kahng, Jiajia Li
2018 J jnl
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li
2017 — conf
Floorplan and placement methodology for improved energy reduction in stacked power-domain design.
ASP-DAC
Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
2017 — —
Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality
Jiajia Li
2017 J jnl
Logic Design Partitioning for Stacked Power Domains.
IEEE Trans. Very Large Scale Integr. Syst.
Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
2017 J jnl
Revisiting 3DIC benefit with multiple tiers.
Integr.
Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
2017 J jnl
Trading Accuracy for Energy in Stochastic Circuit Design.
ACM J. Emerg. Technol. Comput. Syst.
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2016 A* conf
Comprehensive optimization of scan chain timing during late-stage IC implementation.
DAC
Kun Young Chung, Andrew B. Kahng, Jiajia Li
2016 A conf
Improved flop tray-based design implementation for power reduction.
ICCAD
Andrew B. Kahng, Jiajia Li, Lutong Wang
2016 A conf
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking.
DATE
Kwangsoo Han, Andrew B. Kahng, Jiajia Li
2016 A conf
Measuring progress and value of IC implementation technology.
ICCAD
Andrew B. Kahng, Hyein Lee, Jiajia Li
2016 — conf
Revisiting 3DIC Benefit with Multiple Tiers.
SLIP
Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
2015 A* conf
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction.
DAC
Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
2015 J jnl
An Improved Methodology for Resilient Design Implementation.
ACM Trans. Design Autom. Electr. Syst.
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
2015 A conf
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes.
ICCAD
Sorin Dobre, Andrew B. Kahng, Jiajia Li
2015 J jnl
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park
2015 A conf
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs.
ICCAD
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
2014 — conf
A new methodology for reduced cost of resilience.
ACM Great Lakes Symposium on VLSI
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li
2014 — conf
Horizontal benchmark extension for improved assessment of physical CAD research.
ACM Great Lakes Symposium on VLSI
Andrew B. Kahng, Hyein Lee, Jiajia Li
2014 — conf
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation.
ISQED
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
2013 — conf
Optimization of overdrive signoff.
ASP-DAC
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath
2013 — conf
Reliability-constrained die stacking order in 3DICs under manufacturing variability.
ISQED
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
2013 — conf
Toward quantifying the IC design value of interconnect technology improvements.
SLIP
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li