Jiafeng Xie

93 papers A* 4A 5C 10Misc 4Journal 55Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC.
ACM Trans. Reconfigurable Technol. Syst.
Tianyou Bao, Pengzhou He, Daisuke Fujimoto, Yuichi Hayashi, Jiafeng Xie
2025 J jnl
EMINEM: Efficient FPGA Implementation of Mixed-RadIx NTT Hardware AccElerators for NIST Post-QuantuM Cryptography Falcon, Dilithium, and HAWK.
ACM Trans. Reconfigurable Technol. Syst.
Yazheng Tu, Jiafeng Xie
2025 C conf
Efficient Post-Quantum Cryptographic Hardware for Healthcare Applications.
ISCAS
Samuel Coulon, Tianyou Bao, Jiafeng Xie
2025 J jnl
HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography.
ACM Trans. Embed. Comput. Syst.
Pengzhou He, Yazheng Tu, Tianyou Bao, Çetin Kaya Koç, Jiafeng Xie
2025 J jnl
High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC.
IEEE Trans. Very Large Scale Integr. Syst.
Pengzhou He, Tianyou Bao, Jiafeng Xie
2025 J jnl
ISCAS Guest Editorial Special Issue Based on the 2025 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Yuan Du, Xinmiao Zhang
2025 A conf
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON.
ICCAD
Samuel Coulon, Jinjun Xiong, Jiafeng Xie
2025 J jnl
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON.
IACR Cryptol. ePrint Arch.
Samuel Coulon, Jinjun Xiong, Jiafeng Xie
2025 J jnl
LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Yazheng Tu, Tianyou Bao, Pengzhou He, Leonel Sousa, Jiafeng Xie
2025 J jnl
Measuring Computational Universality of Fully Homomorphic Encryption.
CoRR
Jiaqi Xue, Xin Xin, Wei Zhang, Mengxin Zheng, Qianqian Song, Minxuan Zhou, Yushun Dong, Dongjie Wang, Xun Chen, Jiafeng Xie, Liqiang Wang, David Mohaisen, Hongyi Wu, Qian Lou
2025 — ed.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025 - 2 July 2025
ACM Great Lakes Symposium on VLSI
Lu Peng, Boris Vaisband, Fan Chen, Peipei Zhou, Shahar Kvatinsky, Jiafeng Xie
2025 J jnl
SCOPE: Schoolbook-Originated Novel Polynomial Multiplication Accelerators for NTRU-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst.
Yazheng Tu, Shi Bai, Jinjun Xiong, Jiafeng Xie
2024 J jnl
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC.
ACM Trans. Reconfigurable Technol. Syst.
Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto
2024 J jnl
CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Pengzhou He, Samira Carolina Oliva Madrigal, Çetin Kaya Koç, Tianyou Bao, Jiafeng Xie
2024 J jnl
FELIX (XGCD for FALCON): FPGA-based Scalable and Lightweight Accelerator for Large Integer Extended GCD.
IACR Cryptol. ePrint Arch.
Samuel Coulon, Tianyou Bao, Jiafeng Xie
2024 J jnl
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD.
IEEE Trans. Very Large Scale Integr. Syst.
Samuel Coulon, Tianyou Bao, Jiafeng Xie
2024 — conf
HELP: Highly Efficient and Low-Latency Hardware Accelerator for Integer Polynomial Multiplication.
ISVLSI
Pengzhou He, Tianyou Bao, Çetin Kaya Koç, Jiafeng Xie
2024 J jnl
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief.
IEEE Trans. Circuits Syst. II Express Briefs
Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmiao Zhang
2024 A conf
Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach.
ICCAD
Tianyou Bao, Pengzhou He, Jiafeng Xie
2024 — conf
LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC.
ACM Great Lakes Symposium on VLSI
Pengzhou He, Ben Mongirdas, Çetin Kaya Koç, Jiafeng Xie
2024 J jnl
LTE: Lightweight and Time-Efficient Hardware Encoder for Post-Quantum Scheme HQC.
IEEE Comput. Archit. Lett.
Yazheng Tu, Pengzhou He, Chip-Hong Chang, Jiafeng Xie
2024 J jnl
SCALES: SCALable and Area-Efficient Systolic Accelerator for Ternary Polynomial Multiplication.
IEEE Comput. Archit. Lett.
Samuel Coulon, Tianyou Bao, Jiafeng Xie
2024 C conf
SMALL: Scalable Matrix OriginAted Large Integer PoLynomial Multiplication Accelerator for Lattice-Based Post-Quantum Cryptography.
WAIFI
Jiafeng Xie, Pengzhou He, Samira Carolina Oliva Madrigal, Çetin Kaya Koç
2024 J jnl
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst.
Tianyou Bao, Pengzhou He, Shi Bai, Jiafeng Xie
2023 — conf
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC.
ICFPT
Tianyou Bao, Pengzhou He, Jiafeng Xie, H. S. Jacinto
2023 J jnl
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC.
IEEE Trans. Very Large Scale Integr. Syst.
Pengzhou He, Yazheng Tu, Tianyou Bao, Leonel Sousa, Jiafeng Xie
2023 J jnl
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme FALCON.
IACR Cryptol. ePrint Arch.
Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie
2023 Misc conf
Efficient Hardware RNS Decomposition for Post-Quantum Signature Scheme Falcon.
ACSSC
Samuel Coulon, Pengzhou He, Tianyou Bao, Jiafeng Xie
2023 Misc conf
Efficient Implementation of Ring-Binary-LWE-based Lightweight PQC Accelerator on the FPGA Platform.
FCCM
Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
2023 J jnl
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography.
ACM Trans. Reconfigurable Technol. Syst.
Pengzhou He, Tianyou Bao, Jiafeng Xie, Moeness G. Amin
2023 J jnl
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication.
IEEE Comput. Archit. Lett.
Pengzhou He, Yazheng Tu, Çetin Kaya Koç, Jiafeng Xie
2023 J jnl
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography.
IEEE Trans. Very Large Scale Integr. Syst.
Pengzhou He, Yazheng Tu, Jiafeng Xie, H. S. Jacinto
2023 J jnl
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC.
IEEE Trans. Very Large Scale Integr. Syst.
Yazheng Tu, Pengzhou He, Çetin Kaya Koç, Jiafeng Xie
2023 C conf
LOCS: LOw-Latency and ConStant-Timing Implementation of Fixed-Weight Sampler for HQC.
ISCAS
Pengzhou He, Yazheng Tu, Jiafeng Xie
2023 J jnl
Monocular Road Planar Parallax Estimation.
IEEE Trans. Image Process.
Haobo Yuan, Teng Chen, Wei Sui, Jiafeng Xie, Lefei Zhang, Yuan Li, Qian Zhang
2023 — conf
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy.
ISQED
Pengzhou He, Jiafeng Xie
2023 A* conf
PasCore: A Chinese Overlapping Relation Extraction Model Based on Global Pointer Annotation Strategy.
IJCAI
Peng Wang, Jiafeng Xie, Xiye Chen, Guozheng Li, Wei Li
2023 J jnl
VMA: Divide-and-Conquer Vectorized Map Annotation System for Large-Scale Driving Scene.
CoRR
Shaoyu Chen, Yunchi Zhang, Bencheng Liao, Jiafeng Xie, Tianheng Cheng, Wei Sui, Qian Zhang, Chang Huang, Wenyu Liu, Xinggang Wang
2022 J jnl
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking.
J. Electron. Test.
Yadi Zhong, Ayush Jain, M. Tanjidur Rahman, Navid Asadizanjani, Jiafeng Xie, Ujjwal Guin
2022 J jnl
Certificateless signature schemes in Industrial Internet of Things: A comparative survey.
Comput. Commun.
Saddam Hussain, Syed Sajid Ullah, Ihsan Ali, Jiafeng Xie, Venkata N. Inukollu
2022 J jnl
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap.
José Luis Imaña, Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
2022 J jnl
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Emerg. Top. Comput.
Jiafeng Xie, Pengzhou He, Xiaofang Wang, José Luis Imaña
2022 J jnl
Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor.
IEEE Access
Chiou-Yng Lee, Medien Zeghid, Anissa Sghaier, Hassan Yousif Ahmed, Jiafeng Xie
2022 A* conf
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework.
IJCAI
Guozheng Li, Xu Chen, Peng Wang, Jiafeng Xie, Qiqing Luo
2022 J jnl
FastRE: Towards Fast Relation Extraction with Convolutional Encoder and Improved Cascade Binary Tagging Framework.
CoRR
Guozheng Li, Xu Chen, Peng Wang, Jiafeng Xie, Qiqing Luo
2022 — conf
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU.
DFT
Pengzhou He, Yazheng Tu, Ayesha Khalid, Máire O'Neill, Jiafeng Xie
2022 C conf
HPMA-Saber: High-Performance Polynomial Multiplication Accelerator for KEM Saber.
ICCD
Pengzhou He, Tianyou Bao, Yazheng Tu, Jiafeng Xie
2022 C conf
Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber.
ISCAS
Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie
2022 J jnl
High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU.
IACR Cryptol. ePrint Arch.
Elizabeth Carter, Pengzhou He, Jiafeng Xie
2022 J jnl
Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator.
IEEE Comput. Archit. Lett.
Benjamin J. Lucas, Ali Alwan, Marion Murzello, Yazheng Tu, Pengzhou He, Andrew J. Schwartz, David Guevara, Ujjwal Guin, Kyle Juretus, Jiafeng Xie
2022 — conf
Systolic Acceleration of Polynomial Multiplication for KEM Saber and Binary Ring-LWE Post-Quantum Cryptography.
HOST
Tianyou Bao, Pengzhou He, Jiafeng Xie
2022 A conf
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform.
FPGA
Jiafeng Xie, Pengzhou He, Tianyou Bao
2022 Misc conf
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography.
CODES+ISSS
Tianyou Bao, José Luis Imaña, Pengzhou He, Jiafeng Xie
2021 C conf
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy.
ICCD
Jiafeng Xie, Pengzhou He, Chiou-Yng Lee
2021 A* conf
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method.
DAC
Jiafeng Xie, Pengzhou He, Wujie Wen
2021 — conf
FEED: A Chinese Financial Event Extraction Dataset Constructed by Distant Supervision.
IJCKG
Guozheng Li, Peng Wang, Jiafeng Xie, Ruilong Cui, Zhenkai Deng
2021 J jnl
Monocular Road Planar Parallax Estimation.
CoRR
Haobo Yuan, Teng Chen, Wei Sui, Jiafeng Xie, Lefei Zhang, Yuan Li, Qian Zhang
2021 J jnl
Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Pengzhou He, Ujjwal Guin, Jiafeng Xie
2021 — conf
Weibo-MEL, Wikidata-MEL and Richpedia-MEL: Multimodal Entity Linking Benchmark Datasets.
CCKS
Xingchen Zhou, Peng Wang, Guozheng Li, Jiafeng Xie, Jiangheng Wu
2020 — conf
Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2
ASP-DAC
Chiou-Yng Lee, Jiafeng Xie
2020 Misc conf
Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography.
VTS
Jiafeng Xie, Kanad Basu, Kris Gaj, Ujjwal Guin
2019 J jnl
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chiou-Yng Lee, Jiafeng Xie
2019 C conf
Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy.
ICCD
Chiou-Yng Lee, Jiafeng Xie
2019 A conf
Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.
FPGA
Jiafeng Xie, Chiou-Yng Lee
2019 — conf
High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2
HOST
Chiou-Yng Lee, Jiafeng Xie
2019 — conf
LSM: Novel Low-Complexity Unified Systolic Multiplier over Binary Extension Field.
ACM Great Lakes Symposium on VLSI
Jiafeng Xie, Chiou-Yng Lee
2019 C conf
Low-Complexity Systolic Multiplier for GF(2
ISCAS
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher
2019 J jnl
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao
2019 J jnl
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie
2019 A* conf
Predicting Future Instance Segmentation with Contextual Pyramid ConvLSTMs.
ACM Multimedia
Jiangxin Sun, Jiafeng Xie, Jianfang Hu, Zihang Lin, Jianhuang Lai, Wenjun Zeng, Wei-Shi Zheng
2018 J jnl
Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field.
IEEE Access
Chiou-Yng Lee, Chia-Chen Fan, Jiafeng Xie, Shyan-Ming Yuan
2018 A conf
Improving Fast Segmentation With Teacher-Student Learning.
BMVC
Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng
2018 J jnl
Improving Fast Segmentation With Teacher-student Learning.
CoRR
Jiafeng Xie, Bing Shuai, Jianfang Hu, Jingyang Lin, Wei-Shi Zheng
2018 C conf
Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm.
ICCD
Chiou-Yng Lee, Jiafeng Xie
2018 J jnl
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Qiliang Shao, Zhenji Hu, Shaik Nazeem Basha, Zhiping Zhang, Zhiqiang Wu, Chiou-Yng Lee, Jiafeng Xie
2018 J jnl
Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2
IEEE Trans. Multi Scale Comput. Syst.
Jiafeng Xie, Pramod Kumar Meher, Xiaojun Zhou, Chiou-Yng Lee
2018 J jnl
Novel Hybrid-Size Digit-Serial Systolic Multiplier over
Symmetry
Zhenji Hu, Jiafeng Xie
2018 J jnl
Reliable Inversion in GF(2
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehran Mozaffari Kermani, Amir Jalali, Reza Azarderakhsh, Jiafeng Xie, Kim-Kwang Raymond Choo
2017 J jnl
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Mingui Sun, Yuecheng Li, Bo Zeng, Zhi-Hong Mao
2017 — conf
Evaluating obfuscation performance of novel algorithm-to-architecture mapping techniques in systolic-array-based circuits.
AsianHOST
Xiaojun Zhou, Jiafeng Xie
2017 J jnl
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers.
IEEE Trans. Very Large Scale Integr. Syst.
Pingxiuqi Chen, Shaik Nazeem Basha, Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie
2017 J jnl
Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier.
IEEE Trans. Very Large Scale Integr. Syst.
Qiliang Shao, Zhenji Hu, Shaobo Chen, Pingxiuqi Chen, Jiafeng Xie
2016 — conf
Error detection reliable architectures of Camellia block cipher applicable to different variants of its substitution boxes.
AsianHOST
Mehran Mozaffari Kermani, Reza Azarderakhsh, Jiafeng Xie
2015 — conf
FPGA design space exploration of IDEA cryptography IP core.
MWSCAS
Dinesh Varma Penumetcha, Jiafeng Xie, Saiyu Ren
2015 J jnl
High-Throughput Digit-Level Systolic Multiplier Over GF(2
IEEE Trans. Circuits Syst. II Express Briefs
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2015 J jnl
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2015 J jnl
Low-Latency High-Throughput Systolic Multipliers Over GF(2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao
2013 J jnl
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic.
IEEE Trans. Computers
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2013 J jnl
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Jianjun He, Pramod Kumar Meher
2013 J jnl
Low-Complexity Multiplier for GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2012 C conf
Low-latency area-delay-efficient systolic multiplier over GF(2
ISCAS
Jiafeng Xie, Pramod Kumar Meher, Jianjun He
2011 J jnl
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter.
J. Comput.
Jianjun He, Jiafeng Xie
2010 J jnl
FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures.
Microelectron. J.
Jiafeng Xie, Jianjun He, Guanzheng Tan