Jia Yu

11 papers A* 2A 1B 2C 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2012 B conf
Improving the throughput and delay performance of network processors by applying push model.
IWQoS
Bin Liu, Bo Yuan, Huichen Dai, Hongbo Zhao, Jia Yu, Laxmi N. Bhuyan
2010 B conf
Experience on Applying Push Model to Packet Processors in High Performance Routers.
GLOBECOM
Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi N. Bhuyan
2008 C conf
Revisiting the Cache Effect on Multicore Multithreaded Network Processors.
DSD
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan
2007 J jnl
Assertion-Based Design Exploration of DVS in Network Processor Architectures
CoRR
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2007 J jnl
Conserving network processor power consumption by exploiting traffic variability.
ACM Trans. Archit. Code Optim.
Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
2007 A* conf
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining.
DAC
Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang
2005 J jnl
A low energy cache design for multimedia applications exploiting set access locality.
J. Syst. Archit.
Jun Yang, Jia Yu, Youtao Zhang
2005 A conf
Assertion-Based Design Exploration of DVS in Network Processor Architectures.
DATE
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
2005 — conf
Enhancing Network Processor Simulation Speed with Statistical Input Sampling.
HiPEAC
Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan
2005 A* conf
Low power network processor design using clock gating.
DAC
Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
2004 — conf
Assertion-based power/performance analysis of network processor architectures.
HLDVT
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin