Jia Wang

29 papers A* 4A 5C 1Journal 10Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
An Efficient Placement Speedup Technique Based on Graph Signal Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2025 — conf
Enhancing Modern SAT Solver With Machine Learning Method.
ACM Great Lakes Symposium on VLSI
Guanting Chen, Jia Wang
2025 J jnl
The Power of Graph Signal Processing for Chip Placement Acceleration.
CoRR
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024 J jnl
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions.
IEEE Trans. Very Large Scale Integr. Syst.
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2024 A conf
The Power of Graph Signal Processing for Chip Placement Acceleration.
ICCAD
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2023 J jnl
GraphPlanner: Floorplanning with Graph Neural Network.
ACM Trans. Design Autom. Electr. Syst.
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2022 A* conf
Floorplanning with graph attention.
DAC
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
2020 J jnl
KNN-enhanced Deep Learning Against Noisy Labels.
CoRR
Shuyu Kong, You Li, Jia Wang, Amin Rezaei, Hai Zhou
2013 J jnl
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun
2010 A conf
Hybrid energy storage system integration for vehicles.
ISLPED
Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang
2010 — conf
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model.
ASP-DAC
Debasish Das, Jia Wang, Hai Zhou
2009 — conf
Exploring adjacency in floorplanning.
ASP-DAC
Jia Wang, Hai Zhou
2009 J jnl
Gate Sizing by Lagrangian Relaxation Revisited.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jia Wang, Debasish Das, Hai Zhou
2009 — conf
Risk aversion min-period retiming under process variations.
ASP-DAC
Jia Wang, Hai Zhou
2008 A* conf
An efficient incremental algorithm for min-area retiming.
DAC
Jia Wang, Hai Zhou
2008 A conf
Linear constraint graph for floorplan optimization with soft blocks.
ICCAD
Jia Wang, Hai Zhou
2007 — conf
Address generation for nanowire decoders.
ACM Great Lakes Symposium on VLSI
Jia Wang, Ming-Yang Kao, Hai Zhou
2007 A conf
Gate sizing by Lagrangian relaxation revisited.
ICCAD
Jia Wang, Debasish Das, Hai Zhou
2007 J jnl
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jia Wang, Hai Zhou
2007 J jnl
Unified Incremental Physical-Level and High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
2006 J jnl
Clustering for Processing Rate Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Chuan Lin, Jia Wang, Hai Zhou
2006 A* conf
Optimal jumper insertion for antenna avoidance under ratio upper-bound.
DAC
Jia Wang, Hai Zhou
2006 — conf
Processing Rate Optimization by Sequential System Floorplanning.
ISQED
Jia Wang, Hai Zhou, Ping-Chih Wu
2006 — conf
TAPHS: thermal-aware unified physical-level and high-level synthesis.
ASP-DAC
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang
2005 A conf
Clustering for processing rate optimization.
ICCAD
Chuan Lin, Jia Wang, Hai Zhou
2005 A* conf
Incremental exploration of the combined physical and behavioral design space.
DAC
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
2005 — conf
Interconnect estimation without packing via ACG floorplans.
ASP-DAC
Jia Wang, Hai Zhou
2004 C conf
ACG-Adjacent Constraint Graph for General Floorplans.
ICCD
Hai Zhou, Jia Wang
2004 — conf
Minimal period retiming under process variations.
ACM Great Lakes Symposium on VLSI
Jia Wang, Hai Zhou