Ji-Jan Chen

17 papers A 8Misc 2Journal 4Unranked 3
YearRankTypeTitle / Venue / Authors
2015 J jnl
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst.
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013 A conf
Diagnosis and Layout Aware (DLA) scan chain stitching.
ITC
Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan
2013 A conf
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.
ITC
Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
2012 A conf
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
ITC
Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
2011 Misc conf
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
VTS
Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2011 A conf
Black-box leakage power modeling for cell library and SRAM compiler.
DATE
Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen
2010 — conf
A Test Integration Methodology for 3D Integrated Circuits.
Asian Test Symposium
Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010 A conf
An embedded wide-range and high-resolution CLOCK jitter measurement circuit.
DATE
Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen
2010 J jnl
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2008 — conf
Experimental Results of Built-In Jitter Measurement for Gigahertz Clock.
ATS
Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen
2008 J jnl
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu
2007 — conf
A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement.
ATS
Nai-Chen Daniel Cheng, Yu Lee, Ji-Jan Chen
2007 J jnl
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2007 A conf
Diagnosis for MRAM write disturbance fault.
ITC
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2006 A conf
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
ITC
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2005 Misc conf
On A Software-Based Self-Test Methodology and Its Application.
VTS
Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen
2005 A conf
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
ITC
Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen