Jeyavijayan Rajendran

130 papers A* 18A 17B 1C 10Misc 8Journal 60Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	GUIDE: GenAI Units In Digital Design Education. CoRR Weihua Xiao, Jason Blocklove, Matthew DeLorenzo, Johann Knechtel, Ozgur Sinanoglu, Kanad Basu, Jeyavijayan Rajendran, Siddharth Garg, Ramesh Karri
2025	J	`jnl`	Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design. CoRR Matthew DeLorenzo, Kevin Tieu, Prithwish Jana, Piyush Jha, Dileep Kalathil, Vijay Ganesh, Jeyavijayan Rajendran
2025	A*	`conf`	Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs. DAC Sam Bush, Matthew DeLorenzo, Phat Tieu, Jeyavijayan Rajendran
2025	J	`jnl`	Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs. CoRR Sam Bush, Matthew DeLorenzo, Phat Tieu, Jeyavijayan Rajendran
2025	A*	`conf`	GenHuzz: An Efficient Generative Hardware Fuzzer. USENIX Security Symposium Lichao Wu, Mohamadreza Rostami, Huimin Li, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2025	A*	`conf`	LLMPirate: LLMs for Black-box Hardware IP Piracy. NDSS Vasudev Gohil, Matthew DeLorenzo, Veera Vishwa Achuta Sai Venkat Nallam, Joey See, Jeyavijayan Rajendran
2025	J	`jnl`	ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits. CoRR Chen Chen, Zaiyan Xu, Mohamadreza Rostami, David Liu, Dileep Kalathil, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2025	J	`jnl`	Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization. CoRR Fenghua Wu, Evan Pan, Rahul Kande, Michael Quinn, Aakash Tyagi, David Kebo Houngninou, Jeyavijayan Rajendran, Jiang Hu
2025	C	`conf`	Tracing the Logic: Evaluating LLM Reasoning Paths in RTL Generation. ICCD Matthew DeLorenzo, Kevin Tieu, Jeyavijayan Rajendran
2025	—	`conf`	Watermarking LLMs - Challenges and Opportunities in Electronic Design Automation. COINS Matthew DeLorenzo, Phat Tieu, Chen Chen, Vasudev Gohil, Jeyavijayan Rajendran
2024	J	`jnl`	(Security) Assertions by Large Language Models. IEEE Trans. Inf. Forensics Secur. Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri, Jeyavijayan Rajendran
2024	A*	`conf`	AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning. USENIX Security Symposium Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, Jeyavijayan Rajendran
2024	J	`jnl`	AttackGNN: Red-Teaming GNNs in Hardware Security Using Reinforcement Learning. CoRR Vasudev Gohil, Satwik Patnaik, Dileep Kalathil, Jeyavijayan Rajendran
2024	A	`conf`	Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. DATE Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	J	`jnl`	Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing. CoRR Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	J	`jnl`	CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation. CoRR Matthew DeLorenzo, Vasudev Gohil, Jeyavijayan Rajendran
2024	J	`jnl`	DETERRENT: Detecting Trojans Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan Rajendran
2024	J	`jnl`	Enhancing Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Dependent Industrial Infrastructures. IEEE Internet Things J. Peng-Hao Huang, Jaewon Kim, P. R. Kumar, Jeyavijayan Rajendran, Prasad Enjeti
2024	J	`jnl`	Fuzzerfly Effect: Hardware Fuzzing for Memory Safety. CoRR Mohamadreza Rostami, Chen Chen, Rahul Kande, Huimin Li, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	J	`jnl`	Fuzzerfly Effect: Hardware Fuzzing for Memory Safety. IEEE Secur. Priv. Mohamadreza Rostami, Chen Chen, Rahul Kande, Huimin Li, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	J	`jnl`	LLMPirate: LLMs for Black-box Hardware IP Piracy. CoRR Vasudev Gohil, Matthew DeLorenzo, Veera Vishwa Achuta Sai Venkat Nallam, Joey See, Jeyavijayan Rajendran
2024	Misc	`conf`	LLMs for Hardware Security: Boon or Bane? VTS Rahul Kande, Vasudev Gohil, Matthew DeLorenzo, Chen Chen, Jeyavijayan Rajendran
2024	A*	`conf`	Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection. DAC Mohamadreza Rostami, Shaza Zeitouni, Rahul Kande, Chen Chen, Pouya Mahmoody, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	J	`jnl`	Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection. CoRR Mohamadreza Rostami, Shaza Zeitouni, Rahul Kande, Chen Chen, Pouya Mahmoody, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi
2024	A	`conf`	MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. DATE Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2024	J	`jnl`	Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS. CoRR Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil, Shailja Thakur, Ramesh Karri, Siddharth Garg, Jeyavijayan Rajendran
2024	A*	`conf`	ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. DAC Jonathan Hao-Cheng Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, Jeyavijayan Rajendran, Yiran Chen
2024	—	`conf`	Performance Analysis of Zero-Knowledge Proofs. IISWC Saichand Samudrala, Jiawen Wu, Chen Chen, Haoxuan Shan, Jonathan Ku, Yiran Chen, Jeyavijayan Rajendran
2024	J	`jnl`	STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhaokun Han, Aneesh Dixit, Satwik Patnaik, Jeyavijayan Rajendran
2024	A*	`conf`	WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors. USENIX Security Symposium Pallavi Borkar, Chen Chen, Mohamadreza Rostami, Nikhilesh Singh, Rahul Kande, Ahmad-Reza Sadeghi, Chester Rebeiro, Jeyavijayan Rajendran
2024	J	`jnl`	WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors. CoRR Pallavi Borkar, Chen Chen, Mohamadreza Rostami, Nikhilesh Singh, Rahul Kande, Ahmad-Reza Sadeghi, Chester Rebeiro, Jeyavijayan Rajendran
2023	A*	`conf`	FuncTeller: How Well Does eFPGA Hide Functionality? USENIX Security Symposium Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran
2023	J	`jnl`	FuncTeller: How Well Does eFPGA Hide Functionality? CoRR Zhaokun Han, Mohammed Shayan, Aneesh Dixit, Mustafa M. Shihab, Yiorgos Makris, Jeyavijayan Rajendran
2023	A*	`conf`	HyPFuzz: Formal-Assisted Processor Fuzzing. USENIX Security Symposium Chen Chen, Rahul Kande, Nathan Nguyen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2023	J	`jnl`	HyPFuzz: Formal-Assisted Processor Fuzzing. CoRR Chen Chen, Rahul Kande, Nathan Nguyen, Flemming Andersen, Aakash Tyagi, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2023	J	`jnl`	LLM-assisted Generation of Hardware Assertions. CoRR Rahul Kande, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Shailja Thakur, Ramesh Karri, Jeyavijayan Rajendran
2023	J	`jnl`	MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors. CoRR Vasudev Gohil, Rahul Kande, Chen Chen, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2023	A	`conf`	PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. ICCAD Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2023	J	`jnl`	PSOFuzz: Fuzzing Processors with Particle Swarm Optimization. CoRR Chen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2023	J	`jnl`	Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES. CoRR Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran, Jiang Hu
2022	A*	`conf`	ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CCS Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran
2022	J	`jnl`	ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. CoRR Vasudev Gohil, Hao Guo, Satwik Patnaik, Jeyavijayan Rajendran
2022	J	`jnl`	DETERRENT: Detecting Trojans using Reinforcement Learning. CoRR Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan Rajendran
2022	J	`jnl`	Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. IEEE Des. Test Srini Devadas, Jeyavijayan Rajendran
2022	A	`conf`	Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. ICCAD Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava
2022	J	`jnl`	Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. CoRR Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan Rajendran
2022	A*	`conf`	TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. USENIX Security Symposium Rahul Kande, Addison Crump, Garrett Persyn, Patrick Jauernig, Ahmad-Reza Sadeghi, Aakash Tyagi, Jeyavijayan Rajendran
2022	J	`jnl`	TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. CoRR Aakash Tyagi, Addison Crump, Ahmad-Reza Sadeghi, Garrett Persyn, Jeyavijayan Rajendran, Patrick Jauernig, Rahul Kande
2022	J	`jnl`	Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Trans. Emerg. Top. Comput. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2021	J	`jnl`	Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. IEEE Trans. Circuits Syst. II Express Briefs Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio
2021	J	`jnl`	Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. IEEE Trans. Inf. Forensics Secur. Vasudev Gohil, Mark Tressler, Kevin Sipple, Satwik Patnaik, Jeyavijayan Rajendran
2021	—	`conf`	Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned. ACM Great Lakes Symposium on VLSI Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Rahul Kande
2020	J	`jnl`	Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020	J	`jnl`	Breaking Analog Locking Techniques. IEEE Trans. Very Large Scale Integr. Syst. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2020	J	`jnl`	Keynote: A Disquisition on Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak
2020	J	`jnl`	Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Trans. Emerg. Top. Comput. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2020	J	`jnl`	Security of Cloud FPGAs: A Survey. CoRR Chenglu Jin, Vasudev Gohil, Ramesh Karri, Jeyavijayan Rajendran
2020	J	`jnl`	Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu, Wujie Wen, Jeyavijayan Rajendran
2020	—	`book`	Trustworthy Hardware Design: Combinational Logic Locking Techniques Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu
2019	A	`conf`	Breaking Analog Locking Techniques via Satisfiability Modulo Theories. ITC Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2019	A*	`conf`	HardFails: Insights into Software-Exploitable Hardware Bugs. USENIX Security Symposium Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2019	—	`conf`	Layout recognition attacks on split manufacturing. ASP-DAC Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu
2019	C	`conf`	Red Teaming a Multi-Colored Bluetooth Bulb. ICCD Ryan Vrecenar, Michael Hall, Joshua Zshiesche, Mahesh Naidu, Jeyavijayan Rajendran, Stavros Kalafatis
2018	Misc	`conf`	Special session: Recent developments in hardware security. VTS Ro Cammarota, Naghmeh Karimi, Siddharth Garg, Jeyavijayan Rajendran
2018	J	`jnl`	The Cat and Mouse in Split Manufacturing. IEEE Trans. Very Large Scale Integr. Syst. Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran
2018	J	`jnl`	Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IACR Cryptol. ePrint Arch. Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2018	A	`conf`	Towards provably-secure analog and mixed-signal locking against overproduction. ICCAD Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2018	J	`jnl`	When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs. CoRR Ghada Dessouky, David Gens, Patrick Haney, Garrett Persyn, Arun K. Kanuparthi, Hareesh Khattri, Jason M. Fung, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran
2017	—	`conf`	Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization. ASHES@CCS Giovanni Di Crescenzo, Jeyavijayan Rajendran, Ramesh Karri, Nasir D. Memon
2017	C	`conf`	DFS covert channels on multi-core platforms. VLSI-SoC Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani
2017	A	`conf`	Front-end-of-line attacks in split manufacturing. ICCAD Yujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	A*	`conf`	Provably-Secure Logic Locking: From Theory To Practice. CCS Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu
2017	J	`jnl`	Removal Attacks on Logic Locking and Camouflaging Techniques. IACR Cryptol. ePrint Arch. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	—	`conf`	Security analysis of Anti-SAT. ASP-DAC Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	J	`jnl`	Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Trans. Inf. Forensics Secur. Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	—	`conf`	What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	A	`conf`	Activation of logic encrypted chips: Pre-test or post-test? DATE Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu
2016	A	`conf`	CamoPerturb: secure IC camouflaging for minterm protection. ICCAD Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	—	`conf`	Controlling your control flow graph. HOST Arun K. Kanuparthi, Jeyavijayan Rajendran, Ramesh Karri
2016	Misc	`conf`	Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. VLSID Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri
2016	C	`conf`	Hardware-based attacks to compromise the cryptographic security of an election system. ICCD Mohammad-Mahdi Bidmeshki, Gaurav Rajavendra Reddy, Liwei Zhou, Jeyavijayan Rajendran, Yiorgos Makris
2016	C	`conf`	Securing pressure measurements using SensorPUFs. ISCAS Jeyavijayan Rajendran, Jack Tang, Ramesh Karri
2016	J	`jnl`	Security Analysis of Anti-SAT. IACR Cryptol. ePrint Arch. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	A	`conf`	Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect. ICCAD Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran
2016	—	`conf`	Sneak path enabled authentication for memristive crossbar memories. AsianHOST Md. Badruddoja Majumder, Mesbah Uddin, Garrett S. Rose, Jeyavijayan Rajendran
2016	J	`jnl`	Supply-Chain Security of Digital Microfluidic Biochips. Computer Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, Krishnendu Chakrabarty
2016	J	`jnl`	Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging. IACR Cryptol. ePrint Arch. Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	A*	`conf`	The cat and mouse in split manufacturing. DAC Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran
2015	J	`jnl`	Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri
2015	A*	`conf`	Detecting malicious modifications of data in third-party intellectual property cores. DAC Jeyavijayan Rajendran, Vivekananda Vedula, Ramesh Karri
2015	J	`jnl`	Fault Analysis-Based Logic Encryption. IEEE Trans. Computers Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2015	J	`jnl`	Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Trans. Computers Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose
2015	J	`jnl`	Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proc. IEEE Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki
2014	A*	`conf`	A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. DAC Adam Waksman, Jeyavijayan Rajendran, Matthew Suozzo, Simha Sethumadhavan
2014	Misc	`conf`	Hot topic session 9C: Test and fault tolerance for emerging memory technologies. VTS Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran
2014	J	`jnl`	Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2014	J	`jnl`	Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. IEEE Trans. Emerg. Top. Comput. Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri
2014	A	`conf`	Shielding and securing integrated circuits with sensors. ICCAD Davood Shahrjerdi, Jeyavijayan Rajendran, Siddharth Garg, Farinaz Koushanfar, Ramesh Karri
2014	—	`conf`	Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. ISVLSI David H. K. Hoe, Jeyavijayan Rajendran, Ramesh Karri
2013	Misc	`conf`	A study on the effectiveness of Trojan detection techniques using a red team blue team approach. VTS Xuehui Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri
2013	—	`conf`	Hardware security strategies exploiting nanoelectronic circuits. ASP-DAC Garrett S. Rose, Jeyavijayan Rajendran, Nathan R. McDonald, Ramesh Karri, Miodrag Potkonjak, Bryant T. Wysocki
2013	A	`conf`	Hardware security: threat models and metrics. ICCAD Masoud Rostami, Farinaz Koushanfar, Jeyavijayan Rajendran, Ramesh Karri
2013	C	`conf`	High-level synthesis for security and trust. IOLTS Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri
2013	A	`conf`	Is split manufacturing secure? DATE Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2013	B	`conf`	Reconciling the IC test and security dichotomy. ETS Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, Yiorgos Makris
2013	J	`jnl`	Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Des. Test Jeyavijayan Rajendran, Arun K. Kanuparthi, Mohamed Zahran, Sateesh Addepalli, Gaston Ormazabal, Ramesh Karri
2013	A*	`conf`	Security analysis of integrated circuit camouflaging. CCS Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri
2013	—	`conf`	Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. DFTS Chen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri
2013	Misc	`conf`	Sneak-path Testing of Memristor-based Memories. VLSI Design Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
2013	A	`conf`	VLSI testing based security metric for IC camouflaging. ITC Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2012	J	`jnl`	An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Trans. Computers Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2012	J	`jnl`	Design Considerations for Multilevel CMOS/Nano Memristive Memory. ACM J. Emerg. Technol. Comput. Syst. Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose
2012	C	`conf`	Engineering crossbar based emerging memory technologies. ICCD Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
2012	J	`jnl`	Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proc. IEEE Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Robinson E. Pino
2012	A	`conf`	Logic encryption: A fault analysis perspective. DATE Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2012	—	`conf`	Nano-PPUF: A Memristor-Based Security Primitive. ISVLSI Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak
2012	J	`jnl`	Nanoelectronic Solutions for Hardware Security. IACR Cryptol. ePrint Arch. Jeyavijayan Rajendran, Ramesh Karri, James B. Wendt, Miodrag Potkonjak, Nathan R. McDonald, Garrett S. Rose, Bryant T. Wysocki
2012	A*	`conf`	Security analysis of logic obfuscation. DAC Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2012	J	`jnl`	Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Trans. Circuits Syst. I Regul. Pap. Harika Manem, Jeyavijayan Rajendran, Garrett S. Rose
2011	Misc	`conf`	An Approach to Tolerate Process Related Variations in Memristor-Based Applications. VLSI Design Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2011	C	`conf`	Blue team red team approach to hardware trust assessment. ICCD Jeyavijayan Rajendran, Vinayaka Jyothi, Ramesh Karri
2011	Misc	`conf`	Design and analysis of ring oscillator based Design-for-Trust technique. VTS Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri
2011	C	`conf`	Parallel memristors: Improving variation tolerance in memristive digital circuits. ISCAS Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose
2011	J	`jnl`	Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. Computer Mohammad Tehranipoor, Hassan Salmani, Xuehui Zhang, Michel Wang, Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld
2010	—	`conf`	Memristor based programmable threshold logic array. NANOARCH Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose
2010	—	`conf`	SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers. HOST Jeyavijayan Rajendran, Hetal Borad, Shyam Mantravadi, Ramesh Karri
2010	C	`conf`	Towards a comprehensive and systematic classification of hardware Trojans. ISCAS Jeyavijayan Rajendran, Efstratios Gavas, Jorge Jimenez, Vikram Padman, Ramesh Karri
2010	J	`jnl`	Trustworthy Hardware: Identifying and Classifying Hardware Trojans. Computer Ramesh Karri, Jeyavijayan Rajendran, Kurt Rosenfeld, Mohammad Tehranipoor