Jeyavijayan (JV) Rajendran

20 papers A* 4A 3C 2Misc 2Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2025 A* conf
SCONE: A Logic Locking Technique Utilizing SMT Solver and Circuit Encoding Scheme for Efficient Hardware IP Protection.
DAC
Zhaokun Han, Daniel Xing, Kostas Amberiadis, Ankur Srivastava, Jeyavijayan (JV) Rajendran
2023 A* conf
ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning.
DAC
Hao Guo, Sayandeep Saha, Vasudev Gohil, Satwik Patnaik, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran
2022 A* conf
DETERRENT: detecting trojans using reinforcement learning.
DAC
Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan (JV) Rajendran
2022 — conf
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges.
ISOCC
Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan (JV) Rajendran
2022 J jnl
Vulnerability Assessment of Ciphers To Fault Attacks Using Reinforcement Learning.
IACR Cryptol. ePrint Arch.
Hao Guo, Sayandeep Saha, Satwik Patnaik, Vasudev Gohil, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran
2021 A* conf
Does logic locking work with EDA tools?
USENIX Security Symposium
Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran
2021 J jnl
Guest Editors' Introduction: Competing to Secure SoCs.
IEEE Des. Test
Siddharth Garg, Daniel E. Holcomb, Jeyavijayan (JV) Rajendran, Ahmad-Reza Sadeghi
2020 C conf
Multi-Objective Strategies for Stripped-Functionality Logic Locking.
ISCAS
Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran
2020 A conf
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits.
ITC
Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Sir Yee Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran
2019 A conf
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis.
ICCAD
Muhammad Yasin, Chongzhi Zhao, Jeyavijayan (JV) Rajendran
2019 Misc conf
Special Session: Countering IP Security threats in Supply chain.
VTS
Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan (JV) Rajendran, Naghmeh Karimi
2018 A conf
Towards provably-secure performance locking.
DATE
Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran
2017 C conf
An overview of hardware intellectual property protection.
ISCAS
Jeyavijayan (JV) Rajendran
2017 Misc conf
Innovative practices session 3C hardware security.
VTS
Jeyavijayan (JV) Rajendran, Peilin Song, Suriya Natarajan
2017 — conf
On designing optimal camouflaged layouts.
HOST
Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran
2017 — conf
Routing perturbation for enhanced security in split manufacturing.
ASP-DAC
Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran
2017 — conf
TTLock: Tenacious and traceless logic locking.
HOST
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
2016 J jnl
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
2016 J jnl
On Improving the Security of Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
2016 — conf
SARLock: SAT attack resistant logic locking.
HOST
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu