Jeyanandh Paramesh

51 papers A* 1A 1B 1C 4Misc 1Journal 23Unranked 20

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A mm-Wave Wideband Tunable Electrical Balance Duplexer with an Integrated Low-Noise Amplifier in 22-nm CMOS FDSOI. RWS Mohamad Mahdi Rajaei Rizi, Mohammad Ghaedi Bardeh, Jeyanandh Paramesh, Kamran Entesari
2024	J	`jnl`	A 46.6 μg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted Chopper Amplifier. IEEE J. Solid State Circuits Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh
2024	J	`jnl`	System-Level Analysis for mm-Wave Full-Duplex Transceivers. CoRR Mohamad Mahdi Rajaei Rizi, Jeyanandh Paramesh, Kamran Entesari
2023	—	`conf`	A mm-wave RC PPF Quadrature Network with Gain Boosting in 22nm CMOS FDSOI. RWS Mohammad Ghaedi Bardeh, Navid Naseh, Jierui Fu, Jeyanandh Paramesh, Kamran Entesari
2023	—	`conf`	An Efficient Meta-Reinforcement Learning Approach for Circuit Linearity Calibration via Style Injection. MWSCAS Chao Rong, Jeyanandh Paramesh, L. Richard Carley
2022	J	`jnl`	A Deep Reinforcement Learning Framework for High-Dimensional Circuit Linearization. IEEE Trans. Circuits Syst. II Express Briefs Chao Rong, Jeyanandh Paramesh, L. Richard Carley
2022	J	`jnl`	Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems. IEEE J. Solid State Circuits Susnata Mondal, Larry Richard Carley, Jeyanandh Paramesh
2020	—	`conf`	4.4 A 28/37GHz Scalable, Reconfigurable Multi-Layer Hybrid/Digital MIMO Transceiver for TDD/FDD and Full-Duplex Communication. ISSCC Susnata Mondal, L. Richard Carley, Jeyanandh Paramesh
2020	—	`conf`	A Reconfigurable High-Bandwidth CMOS-MEMS Capacitive Accelerometer Array with High-g Measurement Capability and Low Bias Instability. VLSI Circuits Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh
2020	—	`conf`	High-g Capacitive Accelerometer Arrays with Low Bias Instability. PLANS Gary K. Fedder, Vincent P. J. Chung, Metin G. Guney, Xiaoliang Li, Yi-Chung Lin, Suresh Santhanam, Jeyanandh Paramesh, Tamal Mukherjee
2020	A*	`conf`	Millimeter-wave full duplex radios. MobiCom Vaibhav Singh, Susnata Mondal, Akshay Gadre, Milind Srivastava, Jeyanandh Paramesh, Swarun Kumar
2020	J	`jnl`	Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers. IEEE J. Solid State Circuits Susnata Mondal, Jeyanandh Paramesh
2019	—	`conf`	A High Dynamic Range CMOS-MEMS Accelerometer Array with Drift Compensation and Fine-Grain Offset Compensation. CICC Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh
2019	J	`jnl`	A Reconfigurable 28-/37-GHz MMSE-Adaptive Hybrid-Beamforming Receiver for Carrier Aggregation and Multi-Standard MIMO Communication. IEEE J. Solid State Circuits Susnata Mondal, Jeyanandh Paramesh
2019	—	`conf`	A Reconfigurable Bidirectional 28/37/39GHz Front-End Supporting MIMO-TDD, Carrier Aggregation TDD and FDD/Full-Duplex with Self-Interference Cancellation in Digital and Fully Connected Hybrid Beamformers. ISSCC Susnata Mondal, Rahul Singh, Jeyanandh Paramesh
2019	J	`jnl`	An 18 nW -47/-40 dBm Sensitivity 3/100 kbps MEMS-Assisted CMOS Wake-Up Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Mazen Soliman, Abhay Kochhar, Hoda Abdelsalam, Flavius V. Pop, Gabriel Vidal-Álvarez, Jeffrey A. Weldon, Gianluca Piazza, Jeyanandh Paramesh
2018	J	`jnl`	802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano
2018	—	`conf`	A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS. ESSCIRC Shaolong Liu, Jeyanandh Paramesh, Larry T. Pileggi, Taimur Gibran Rabuske, Jorge Fernandcs
2018	J	`jnl`	A 25-30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication. IEEE J. Solid State Circuits Susnata Mondal, Rahul Singh, Ahmed I. Hussein, Jeyanandh Paramesh
2018	J	`jnl`	A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs. IEEE J. Solid State Circuits Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh
2018	—	`conf`	A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation. ISSCC Susnata Mondal, Rahul Singh, Jeyanandh Paramesh
2018	J	`jnl`	Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes
2017	—	`conf`	19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter. ISSCC Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh
2017	J	`jnl`	A 50-66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs. IEEE J. Solid State Circuits Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh
2017	C	`conf`	A four-antenna baseband multipath emulator for millimeter-wave channels. ISCAS Mazen Soliman, Shih-Chang Hung, Jeyanandh Paramesh
2017	J	`jnl`	Design and Self-Calibration Techniques for Inductor-Less Millimeter-Wave Frequency Dividers. IEEE J. Solid State Circuits Ahmed I. Hussein, Jeyanandh Paramesh
2017	J	`jnl`	Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A. IEEE Trans. Circuits Syst. I Regul. Pap. Sandipan Kundu, Subhanshu Gupta, David J. Allstot, Jeyanandh Paramesh
2015	J	`jnl`	A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN. IEEE Trans. Circuits Syst. I Regul. Pap. Sandipan Kundu, Erkan Alpman, Julia Hsin-Lin Lu, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon
2015	—	`conf`	A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularity. CICC Ahmed I. Hussein, Shadi Saberi, Jeyanandh Paramesh
2015	J	`jnl`	A Compact, Supply-Voltage Scalable 45-66 GHz Baseband-Combining CMOS Phased-Array Receiver. IEEE J. Solid State Circuits Sandipan Kundu, Jeyanandh Paramesh
2015	B	`conf`	Adaptive Beamforming Assisted Decision Feedback Equalization for Millimeter Wave Receivers. GLOBECOM Ahmed I. Hussein, Sandipan Kundu, Jeyanandh Paramesh
2015	—	`conf`	DAC mismatch shaping for quadrature sigma-delta data converters. MWSCAS Sandipan Kundu, Subhanshu Gupta, David J. Allstot, Jeyanandh Paramesh
2015	A	`conf`	Statistical Learning in Chip (SLIC). ICCAD Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2014	—	`conf`	A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN. CICC Sandipan Kundu, Julia Hsin-Lin Lu, Erkan Alpman, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon
2014	—	`conf`	SLIC: Statistical learning in chip. ISIC Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2013	—	`conf`	A stepped-frequency continuous wave ranger for aiding pedestrian navigation. WiSNet James Downey, Jeyanandh Paramesh, Daniel D. Stancil, Tamal Mukherjee
2013	—	`conf`	Ultra-low power frequency and duty-cycle modulated implantable pressure-temperature sensor. BioCAS Ahmad Khairi, Chenyang Wu, Yoed Rabin, Gary K. Fedder, Jeyanandh Paramesh, David Schwartzman
2012	—	`conf`	A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication. CICC Sandipan Kundu, Ahmad Khairi, Jeyanandh Paramesh
2012	—	`conf`	Low-power front-end amplification and frequency generation techniques for ultra-wideband millimeter-wave transceivers. MWSCAS Jeyanandh Paramesh, Sandipan Kundu, Shadi Saberi
2012	J	`jnl`	Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs. J. Signal Process. Syst. Subhanshu Gupta, Yi Tang, Jeyanandh Paramesh, David J. Allstot
2011	Misc	`conf`	Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems. ICASSP Subhanshu Gupta, Yi Tang, Kuang-Wei Cheng, Jeyanandh Paramesh, David J. Allstot
2011	—	`conf`	Post-silicon calibration of analog CMOS using phase-change memory cells. ESSCIRC Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, Sangbum Kim, Jonathan E. Proesel, Chung Lam
2009	J	`jnl`	Integrated Quadrature Couplers and Their Application in Image-Reject Receivers. IEEE J. Solid State Circuits Dicle Ozis, Jeyanandh Paramesh, David J. Allstot
2008	J	`jnl`	Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. Yi Tang, Kuang-Wei Cheng, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot
2008	C	`conf`	Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators. ISCAS Subhanshu Gupta, Yi Tang, David J. Allstot, Jeyanandh Paramesh
2007	C	`conf`	A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC. ISCAS Yi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot
2006	J	`jnl`	A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion. IEEE J. Solid State Circuits Mostafa Elmala, Jeyanandh Paramesh, Krishnamurthy Soumyanath
2006	C	`conf`	Analysis and design of lumped-element quadrature couplers with lossy passive elements. ISCAS Dicle Ozis, Jeyanandh Paramesh, David J. Allstot
2006	J	`jnl`	Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem. IEEE Trans. Circuits Syst. II Express Briefs Jeyanandh Paramesh, David J. Allstot
2005	J	`jnl`	A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity. IEEE J. Solid State Circuits Jeyanandh Paramesh, Ralph Bishop, Krishnamurthy Soumyanath, David J. Allstot
2001	J	`jnl`	Use of sigma-delta modulation to control EMI from switch-mode power supplies. IEEE Trans. Ind. Electron. Jeyanandh Paramesh, Annette R. von Jouanne