Jerzy Tyszer - RankMe

161 papers A* 5A 44B 13C 2Misc 18Journal 70Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2025	A	`conf`	Automated Selection of Optimal EDT Input Configuration. ITC Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2025	J	`jnl`	Hybrid Ring Generators for In-System Testing. J. Electron. Test. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2025	B	`conf`	Identification of Failing Flip-Flops with Triangular Test Response Compaction. ETS Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2025	J	`jnl`	On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024	A	`conf`	Deterministic In-Fleet Scan Test for a Cloud Computing Platform. ITC Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer
2024	J	`jnl`	H IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024	A	`conf`	Test Data Encryption with a New Stream Cipher. ITC Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2024	J	`jnl`	The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
2023	J	`jnl`	A Lightweight True Random Number Generator for Root of Trust Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2023	J	`jnl`	A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2023	B	`conf`	Hybrid Ring Generators for In-System Test Applications. ETS Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2023	J	`jnl`	X-Masking for Deterministic In-System Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2022	A	`conf`	DIST: Deterministic In-System Test with X-masking. ITC Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2022	A	`conf`	Hardware Root of Trust for SSN-basedDFT Ecosystems. ITC Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak
2022	J	`jnl`	LBIST for Automotive ICs With Enhanced Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2022	B	`conf`	X-Masking for In-System Deterministic Test. ETS Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2021	J	`jnl`	Autonomous Scan Patterns for Laser Voltage Imaging. IEEE Trans. Emerg. Top. Comput. Wu-Tung Cheng, Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2021	B	`conf`	Convolutional Compaction-Based MRAM Fault Diagnosis. ETS Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2021	A	`conf`	On Reduction of Deterministic Test Pattern Sets. ITC Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2021	J	`jnl`	Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2021	J	`jnl`	X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. IEEE Trans. Very Large Scale Integr. Syst. Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak
2020	J	`jnl`	Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2020	J	`jnl`	Low Cost Hypercompression of Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2020	J	`jnl`	Scan Integrity Tests for EDT Compression. IEEE Des. Test Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2020	B	`conf`	Test Sequence-Optimized BIST for Automotive Applications. ETS Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
2020	A	`conf`	X-Tolerant Tunable Compactor for In-System Test. ITC Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak
2019	J	`jnl`	Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2019	Misc	`conf`	On Cyclic Scan Integrity Tests for EDT-based Compression. VTS Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer
2019	A	`conf`	Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki
2018	A	`conf`	Deterministic Stellar BIST for In-System Automotive Test. ITC Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer
2018	J	`jnl`	Hardware Protection via Logic Locking Test Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Chen, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2018	A	`conf`	Hypercompression of Test Patterns. ITC Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang
2018	A	`conf`	On New Class of Test Points and Their Applications. ITC Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2018	Misc	`conf`	Staggered ATPG with capture-per-cycle observation test points. VTS Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer
2017	J	`jnl`	Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada
2017	A	`conf`	Full-scan LBIST with capture-per-cycle hybrid test points. ITC Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
2017	B	`conf`	ROM fault diagnosis for O(n ETS Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2017	J	`jnl`	Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
2017	J	`jnl`	Trimodal Scan-Based Test Paradigm. IEEE Trans. Very Large Scale Integr. Syst. Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
2016	A	`conf`	Minimal area test points for deterministic patterns. ITC Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer
2016	J	`jnl`	On New Test Points for Compact Cell-Aware Tests. IEEE Des. Test Cesar Acero, Derek Feltham, Marek Patyra, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	—	`conf`	On Test Points Enhancing Hardware Security. ATS Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2016	A	`conf`	Test point insertion in hybrid test compression/LBIST architectures. ITC Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2015	A	`conf`	A deterministic BIST scheme based on EDT-compressed test patterns. ITC Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer
2015	A*	`conf`	Design for low test pattern counts. DAC Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada
2015	A	`conf`	Embedded deterministic test points for compact cell-aware tests. ITC Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada
2015	J	`jnl`	Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2015	J	`jnl`	Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2015	J	`jnl`	Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2015	—	`conf`	TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm. ATS Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Chen Wang
2014	J	`jnl`	Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	—	`conf`	High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2014	A	`conf`	Isometric test compression with low toggling activity. ITC Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014	—	`conf`	Low Power Test Compression with Programmable Broadcast-Based Control. ATS Sylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2014	A*	`conf`	On Using Implied Values in EDT-based Test Compression. DAC Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	C	`conf`	Quality assurance in memory built-in self-test tools. DDECS Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada
2013	A	`conf`	EDT bandwidth management - Practical scenarios for large SoC designs. ITC Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013	A	`conf`	Fault diagnosis of TSV-based interconnects in 3-D stacked designs. ITC Janusz Rajski, Jerzy Tyszer
2013	B	`conf`	New test compression scheme based on low power BIST. ETS Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2013	J	`jnl`	On Deploying Scan Chains for Data Storage in Test Compression Environment. IEEE Des. Test Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2013	J	`jnl`	Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	B	`conf`	Bandwidth-aware test compression logic for SoC designs. ETS Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski
2012	J	`jnl`	EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	A	`conf`	Low power programmable PRPG with enhanced fault coverage gradient. ITC Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2012	A	`conf`	Low power test application with selective compaction in VLSI designs. ITC Dariusz Czysz, Janusz Rajski, Jerzy Tyszer
2012	Misc	`conf`	Test generator with preselected toggling for low power built-in self-test. VTS Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
2011	J	`jnl`	BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2011	J	`jnl`	Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2011	B	`conf`	Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. ETS Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2011	A	`conf`	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2011	—	`conf`	Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek
2011	J	`jnl`	Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electron. Test. Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2011	—	`conf`	Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer
2011	—	`conf`	Power Aware Embedded Test. Asian Test Symposium Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
2011	B	`conf`	Reduced ATE Interface for High Test Data Compression. ETS Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2011	J	`jnl`	Ring Generator: An Ultimate Linear Feedback Shift Register. Computer Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer
2010	B	`conf`	Diagnosis of failing scan cells through orthogonal response compaction. ETS Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer
2010	A	`conf`	Dynamic channel allocation for higher EDT compression in SoC designs. ITC Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2010	J	`jnl`	High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2010	A	`conf`	Low power compression of incompatible test cubes. ITC Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
2010	J	`jnl`	On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	Compression based on deterministic vector clustering of incompatible test cubes. ITC Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009	Misc	`conf`	Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2009	A	`conf`	Fault diagnosis for embedded read-only memories. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2009	Misc	`conf`	Highly X-Tolerant Selective Compaction of Test Responses. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2009	J	`jnl`	Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	A	`conf`	High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2008	A	`conf`	Low Power Scan Shift and Capture in the EDT Environment. ITC Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	J	`jnl`	Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	J	`jnl`	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2007	J	`jnl`	Fault Diagnosis With Convolutional Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2007	J	`jnl`	Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electron. Test. Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer
2007	Misc	`conf`	Low Power Embedded Deterministic Test. VTS Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2007	A*	`conf`	New Test Data Decompressor for Low Power Applications. DAC Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
2007	J	`jnl`	X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006	B	`conf`	Convolutional Compactors with Variable Polynomials. ETS Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2006	J	`jnl`	High Performance Dense Ring Generators. IEEE Trans. Computers Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2006	A*	`conf`	Test response compactor with programmable selector. DAC Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2006	A	`conf`	X-Press Compactor for 1000x Reduction of Test Data. ITC Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2005	B	`conf`	Convolutional compaction-driven diagnosis of scan failures. ETS Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang
2005	A	`conf`	Diagnosis with convolutional compactors in presence of unknown states. ITC Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer
2005	J	`jnl`	Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2005	Misc	`conf`	On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz
2005	Misc	`conf`	Synthesis of X-Tolerant Convolutional Compactors. VTS Janusz Rajski, Jerzy Tyszer
2004	Misc	`conf`	Embedded Test for Low Cost Manufacturing. VLSI Design Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht
2004	J	`jnl`	Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
2004	A	`conf`	Fault Diagnosis in Designs with Convolutional Compactors. ITC Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski
2004	Misc	`conf`	Planar High Performance Ring Generators. VTS Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2004	J	`jnl`	Ring generators - new devices for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	2D Test Sequence Generators. IEEE Des. Test Comput. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
2003	A	`conf`	Convolutional Compaction of Test Responses. ITC Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy
2003	J	`jnl`	Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
2003	Misc	`conf`	High Speed Ring Generators and Compactors of Test Data. VTS Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2003	A	`conf`	On Compacting Test Response Data Containing Unknown Values. ICCAD Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer
2003	J	`jnl`	Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. J. Electron. Test. Janusz Rajski, Jerzy Tyszer
2003	C	`conf`	Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. ICCD Janusz Rajski, Jerzy Tyszer
2002	A	`conf`	Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
2001	J	`jnl`	Testing Schemes for FIR Filter Structures. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2000	J	`jnl`	Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
2000	J	`jnl`	Cellular automata-based test pattern generators with phase shifters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2000	Misc	`conf`	Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
1999	Misc	`conf`	Built-In Self-Test for Systems on Silicon. VLSI Design Janusz Rajski, Jerzy Tyszer, Sanjay Patel
1999	Misc	`conf`	Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer
1999	J	`jnl`	Diagnosis of Scan Cells in BIST Environment. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1999	A	`conf`	Synthesis of pattern generators based on cellular automata with phase shifters. ITC Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
1999	J	`jnl`	Testing of telecommunications hardware [Guest Editorial]. IEEE Commun. Mag. Janusz Rajski, Jerzy Tyszer
1998	A	`conf`	Automated synthesis of large phase shifters for built-in self-test. ITC Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer
1998	Misc	`conf`	Design of Phase Shifters for BIST Applications. VTS Janusz Rajski, Jerzy Tyszer
1998	A	`conf`	Modular logic built-in self-test for IP cores. ITC Janusz Rajski, Jerzy Tyszer
1998	J	`jnl`	Test Data Decompression for Multiple Scan Designs with Boundary Scan. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer, Nadime Zacharia
1997	J	`jnl`	Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer
1997	J	`jnl`	Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997	A	`conf`	Fault Diagnosis in Scan-Based BIST. ITC Janusz Rajski, Jerzy Tyszer
1997	A	`conf`	Parameterizable Testing Scheme for FIR Filters. ITC Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1996	J	`jnl`	Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. IEEE Trans. Computers Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
1996	J	`jnl`	Broadband Time-Division Circuit Switching. IEEE J. Sel. Areas Commun. Andrzej Jajszczyk, Jerzy Tyszer
1996	—	`conf`	Multiplicative Window Generators of Pseudo-random Test Vectors. ED&TC Janusz Rajski, Jerzy Tyszer
1996	J	`jnl`	On Linear Dependencies in Subspaces of LFSR-Generated Sequences. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1996	A	`conf`	Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
1995	Misc	`conf`	Arithmetic built-in self test for high-level synthesis. VTS Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer
1995	Misc	`conf`	Decompression of test data using variable-length seed LFSRs. VTS Nadime Zacharia, Janusz Rajski, Jerzy Tyszer
1995	A	`conf`	Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC Mark Kassab, Janusz Rajski, Jerzy Tyszer
1995	A	`conf`	On testable multipliers for fixed-width data path architectures. ICCAD Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1995	A*	`conf`	Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1994	A	`conf`	Test pattern generation based on arithmetic operations. ICCAD Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Accumulator-Based Compaction of Test Responses. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Recursive Pseudoexhaustive Test Pattern Generation. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1993	J	`jnl`	Test responses compaction in accumulators with rotate carry adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer
1992	J	`jnl`	Testing of three-stage switching networks for coupling faults. IEEE Trans. Commun. Jerzy Tyszer
1991	J	`jnl`	On the diagnostic properties of linear feedback shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer
1991	J	`jnl`	Test generation for pattern-sensitive faults in integrated switches. IEEE Trans. Commun. Jerzy Tyszer
1990	J	`jnl`	Interference faults testing for time switches. IEEE Trans. Commun. Jerzy Tyszer
1990	A	`conf`	On the Diagnostic Resolution of Signature Analysis. ICCAD Janusz Rajski, Jerzy Tyszer, Babak Salimi
1989	J	`jnl`	Fault diagnosis of digital switching networks. IEEE Trans. Commun. Andrzej Jajszczyk, Jerzy Tyszer
1988	J	`jnl`	A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing. IEEE Trans. Computers Jerzy Tyszer
1988	J	`jnl`	Multiple fault diagnosis for interconnection networks for distributed systems. Microprocess. Microprogramming Jerzy Tyszer
1986	J	`jnl`	The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1985	J	`jnl`	Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. IEEE Trans. Computers Janusz Rajski, Jerzy Tyszer
1984	—	`conf`	The detection of small size multiple faults by single fault test sets n programmable logic arrays. Fehlertolerierende Rechensysteme Janusz Rajski, Jerzy Tyszer