Jerzy J. Dabrowski

33 papers A 2C 4Journal 10Unranked 17
YearRankTypeTitle / Venue / Authors
2020 J jnl
One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC Test.
J. Circuits Syst. Comput.
Shakeel Ahmad, Jerzy J. Dabrowski
2019 J jnl
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test.
J. Electron. Test.
Shakeel Ahmad, Jerzy J. Dabrowski
2016 J jnl
Tunable selective receiver front end with impedance transformation filtering.
Int. J. Circuit Theory Appl.
Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski
2015 — conf
Clock phase imbalance and phase noise in RF N-path filters.
ECCTD
Fahad Qazi, Jerzy J. Dabrowski
2015 J jnl
Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Fahad Qazi, Jerzy J. Dabrowski
2015 J jnl
RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique.
Integr.
Rashad Ramzan, Jerzy J. Dabrowski
2015 J jnl
Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering.
IEEE Trans. Circuits Syst. II Express Briefs
Fahad Quiz, Quoc-Tai Duong, Jerzy J. Dabrowski
2013 — conf
Blocker and image reject low-IF frontend.
ECCTD
Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski
2013 — conf
Focused calibration for advanced RF test with embedded RF detectors.
ECCTD
Quoc-Tai Duong, Jerzy J. Dabrowski
2013 — conf
Highly linear open-loop output driver design for high speed capacitive DACs.
NORCHIP
Quoc-Tai Duong, Jerzy J. Dabrowski, Atila Alvandpour
2012 — conf
Wideband RF detector design for high performance on-chip test.
NORCHIP
Quoc-Tai Duong, Jerzy J. Dabrowski
2011 — conf
Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend.
ECCTD
Quoc-Tai Duong, Jerzy J. Dabrowski
2011 — conf
On-chip spectral test for high-speed ADCs by ΣΔ technique.
ECCTD
Shakeel Ahmad, Jerzy J. Dabrowski
2010 J jnl
Built-in Loopback Test for IC RF Transceivers.
IEEE Trans. Very Large Scale Integr. Syst.
Jerzy J. Dabrowski, Rashad Ramzan
2010 J jnl
On-Chip Stimulus Generator for Gain, Linearity, and Blocking Profile Test of Wideband RF Front Ends.
IEEE Trans. Instrum. Meas.
Rashad Ramzan, N. Ahsan, Jerzy J. Dabrowski
2010 C conf
Two-tone PLL for on-chip IP3 test.
ISCAS
Shakeel Ahmad, Kaveh Azizi, Iman Esmaeil Zadeh, Jerzy J. Dabrowski
2009 — conf
On-chip stimuli generation for ADC dynamic test by ΣΔ technique.
ECCTD
Shakeel Ahmad, Jerzy J. Dabrowski
2007 — conf
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.
ISSCC
Rashad Ramzan, Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson
2007 A conf
Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique.
DATE
Jerzy J. Dabrowski, Rashad Ramzan
2007 — conf
Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.
ECCTD
Stefan Back Andersson, Rashad Ramzan, Jerzy J. Dabrowski, Christer Svensson
2006 C conf
LNA design for on-chip RF test.
ISCAS
Rashad Ramzan, Lei Zou, Jerzy J. Dabrowski
2006 C conf
SC filter for RF down conversion with wideband image rejection.
ISCAS
Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson, J. Konopacki
2005 J jnl
A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS.
IEEE J. Solid State Circuits
Darius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson
2005 — conf
Techniques for sensitizing RF path under SER test.
ISCAS (5)
Jerzy J. Dabrowski, Javier Gonzalez Bayon
2004 — conf
Fault modeling of RF blocks based on noise analysis.
ISCAS (1)
Jerzy J. Dabrowski
2004 — conf
Mixed Loopback BiST for RF Digital Transceivers.
DFT
Jerzy J. Dabrowski, Javier Gonzalez Bayon
2003 — conf
BiST Model for IC RF-Transceiver Front-End.
DFT
Jerzy J. Dabrowski
2003 — conf
Lookback BiST for RF front-ends in digital transceivers.
SoC
Jerzy J. Dabrowski
2002 — conf
Efficient post-layout timing verification via RLC trees and explicit PWL timing integration.
ICECS
Jerzy J. Dabrowski
2000 C conf
Efficient interconnect timing analysis via piecewise linear technique.
ISCAS
Jerzy J. Dabrowski
1999 A conf
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique.
DATE
Jerzy J. Dabrowski, Andrzej Pulka
1995 — conf
Functional-level analog macromodeling with piecewise linear signals.
EURO-DAC
Jerzy J. Dabrowski
1992 J jnl
Efficient timing verification via mixed-mode technique.
Microprocess. Microprogramming
Jerzy J. Dabrowski