Jerry R. Burch

35 papers A* 9A 6B 1C 2Misc 2Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2007	A*	`conf`	Memory Modeling in ESL-RTL Equivalence Checking. DAC Alfred Kölbl, Jerry R. Burch, Carl Pixley
2007	J	`jnl`	Refinement preserving approximations for the design and verification of heterogeneous systems. Formal Methods Syst. Des. Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
2006	J	`jnl`	Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2006	J	`jnl`	Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2005	—	`conf`	Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2004	Misc	`conf`	Conservative approximations for heterogeneous design. EMSOFT Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
2001	—	`conf`	Constraints specification at higher levels of abstraction. HLDVT Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
2001	—	`conf`	Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. ACSD Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
2001	Misc	`conf`	Using Multiple Levels of Abstractions in Embedded Software Design. EMSOFT Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
2000	J	`jnl`	Sibling-substitution-based BDD minimization using don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
1998	J	`jnl`	Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods Syst. Des. Peter A. Beerel, Jerry R. Burch, Teresa H. Meng
1998	A	`conf`	Robust latch mapping for combinational equivalence checking. ICCAD Jerry R. Burch, Vigyan Singhal
1998	A	`conf`	Tight integration of combinational verification methods. ICCAD Jerry R. Burch, Vigyan Singhal
1997	A*	`conf`	Safe BDD Minimization Using Don't Cares. DAC Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
1996	B	`conf`	Mechanically Checking a Lemma Used in an Automatic Verification Tool. FMCAD Phillip J. Windley, Jerry R. Burch
1996	A*	`conf`	Techniques for Verifying Superscalar Microprocessors. DAC Jerry R. Burch
1995	A	`conf`	Efficient validity checking for processor verification. ICCAD Robert B. Jones, David L. Dill, Jerry R. Burch
1994	A*	`conf`	Automatic verification of Pipelined Microprocessor Control. CAV Jerry R. Burch, David L. Dill
1994	—	`conf`	Sufficient conditions for correct gate-level speed-independent circuits. ASYNC Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng
1994	J	`jnl`	Symbolic model checking for sequential circuit verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill
1993	A	`conf`	Efficient verification of determinate speed-independent circuits. ICCAD Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng
1993	A	`conf`	Modeling hierarchical combinational circuits. ICCAD Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
1992	C	`conf`	Delay Models for Verifying Speed-Dependent Asynchronous Circuits. ICCD Jerry R. Burch
1992	A	`conf`	Efficient Boolean function matching. ICCAD Jerry R. Burch, David E. Long
1992	J	`jnl`	Symbolic Model Checking: 10^20 States and Beyond Inf. Comput. Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
1991	A*	`conf`	Representing Circuits More Efficiently in Symbolic Model Checking. DAC Jerry R. Burch, Edmund M. Clarke, David E. Long
1991	—	`conf`	Symbolic Model Checking with Partitioned Transistion Relations. VLSI Jerry R. Burch, Edmund M. Clarke, David E. Long
1991	A*	`conf`	Using BDDs to Verify Multipliers. DAC Jerry R. Burch
1990	A*	`conf`	Sequential Circuit Verification Using Symbolic Model Checking. DAC Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill
1990	A*	`conf`	Symbolic Model Checking: 10^20 States and Beyond LICS Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
1990	A*	`conf`	Verifying Liveness Properties by Verifying Safety Properties. CAV Jerry R. Burch
1990	—	`conf`	Verifying Liveness Properties by Verifying Safety Properties. CAV (DIMACS/AMS volume) Jerry R. Burch
1989	—	`conf`	Combining CTL, Trace Theory and Timing Models. Automatic Verification Methods for Finite State Systems Jerry R. Burch
1989	C	`conf`	Modeling timing assumptions with trace theory. ICCD Jerry R. Burch
1985	J	`jnl`	Fair Mutual Exclusion with Unfair P and V Operations. Inf. Process. Lett. Alain J. Martin, Jerry R. Burch