Jeremy Yung Shern Low

15 papers C 4Journal 7Unranked 4
YearRankTypeTitle / Venue / Authors
2016 J jnl
Erratum to "Efficient VLSI Implementation of 2
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2013 J jnl
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeremy Yung Shern Low, Chip-Hong Chang
2013 C conf
A signed integer programmable power-of-two scaler for {2
ISCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2013 J jnl
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst.
Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low
2012 J jnl
A VLSI Efficient Programmable Power-of-Two Scaler for 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Jeremy Yung Shern Low, Chip-Hong Chang
2012 — conf
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion.
APCCAS
Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang
2012 C conf
A fast and compact circuit for integer square root computation based on Mitchell logarithmic method.
ISCAS
Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2012 — conf
A unified {2
APCCAS
Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang
2011 C conf
A new RNS scaler for {2
ISCAS
Jeremy Yung Shern Low, Chip-Hong Chang
2011 J jnl
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong, Xiaoliang Tan, Kiat Seng Yeo
2011 J jnl
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo, Jeremy Yung Shern Low
2011 J jnl
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Jeremy Yung Shern Low
2010 C conf
A novel counter-based low complexity inner-product architecture for high speed inputs.
ISCAS
Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low
2010 — conf
An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving.
APCCAS
Anh-Tuan Do, Kiat Seng Yeo, Jeremy Yung Shern Low, Joshua Yung Lih Low, Zhi-Hui Kong
2008 — conf
A full current-mode sense amplifier for low-power SRAM applications.
APCCAS
Anh-Tuan Do, Jeremy Yung Shern Low, Zhi-Hui Kong, Kiat Seng Yeo, Joshua Yung Low Yung Lih