Jer-Min Jou

32 papers A* 1A 3C 5Journal 14Unranked 9
YearRankTypeTitle / Venue / Authors
2014 A conf
A Run-time Manager for Multithreading of Multi-core Systems.
ICS
Cheng-Hung Hsieh, Jer-Min Jou
2014 A conf
A Transaction-based Design Model and Its MPEG-2 Encoder Design.
ICS
Chun-Yu Chen, Yun-Lung Lee, Jer-Min Jou
2011 J jnl
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
2010 J jnl
An Optimal Round-Robin Arbiter Design for NoC.
J. Inf. Sci. Eng.
Jer-Min Jou, Yun-Lung Lee
2010 — conf
Efficient design and generation of a multi-facet arbiter.
SASP
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
2010 A* conf
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.
DAC
Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang
2009 C conf
A high-speed and decentralized arbiter design for NoC.
AICCSA
Yun-Lung Lee, Jer-Min Jou, Yen-Yu Chen
2007 — conf
A Novel Reconfigurable Computation Unit for DSP Applications.
ISVLSI
Jer-Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun
2005 J jnl
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang
2004 J jnl
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme.
IEICE Trans. Inf. Syst.
Yeu-Horng Shiau, Jer-Min Jou, Chin-Chi Liu
2002 J jnl
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. Very Large Scale Integr. Syst.
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
2001 — conf
An efficient VLSI architecture for HMM-based speech recognition.
ICECS
Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang
2001 J jnl
An efficient blocking-matching algorithm based on fuzzy reasoning.
IEEE Trans. Syst. Man Cybern. Part B
Pei-Yin Chen, Jer-Min Jou
2001 — conf
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.
ISCAS (2)
Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu
2000 J jnl
Adaptive arithmetic coding using fuzzy reasoning and grey prediction.
Fuzzy Sets Syst.
Pei-Yin Chen, Jer-Min Jou
2000 J jnl
An adaptive fuzzy logic controller: its VLSI architecture and applications.
IEEE Trans. Very Large Scale Integr. Syst.
Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang
1999 — conf
A New Pipelined Architecture for Fuzzy Color Correction.
ASP-DAC
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau
1999 — conf
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
ASP-DAC
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang
1999 J jnl
A fast and efficient lossless data-compression method.
IEEE Trans. Commun.
Jer-Min Jou, Pei-Yin Chen
1999 — conf
A grey prediction motion estimator for digital image processing.
ICECS
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun
1999 — conf
An efficient method for the decomposition and resynthesis of speed-independent circuits.
ICECS
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
1999 — conf
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
ASP-DAC
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
1999 J jnl
The gray prediction search algorithm for block motion estimation.
IEEE Trans. Circuits Syst. Video Technol.
Jer-Min Jou, Pei-Yin Chen, Jian-Ming Sun
1997 J jnl
Diagnostic fault simulation for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shung-Chih Chen, Jer-Min Jou
1997 J jnl
Serial diagnostic fault simulation for synchronous sequential circuits.
Integr.
Shung-Chih Chen, Jer-Min Jou
1995 C conf
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.
ISCAS
Jer-Min Jou, Shung-Chih Chen
1994 C conf
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits.
ISCAS
Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen
1994 A conf
A fast and memory-efficient diagnostic fault simulation for sequential circuits.
ICCAD
Jer-Min Jou, Shung-Chih Chen
1994 C conf
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
ISCAS
Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang
1993 C conf
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
ICCD
Jer-Min Jou, Shiann-Rong Kuang
1990 J jnl
An Efficient VLSI Switch-Box Router.
IEEE Des. Test Comput.
Jer-Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang
1989 J jnl
A new 3-layer rectilinear area router with obstacle avoidance.
Integr.
Jer-Min Jou, Jau-Yien Lee