Jens Leenstra

23 papers A* 3A 5C 1Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2015 J jnl
Advanced features in IBM POWER8 systems.
IBM J. Res. Dev.
Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block
2015 J jnl
IBM POWER8 processor core microarchitecture.
IBM J. Res. Dev.
Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler
2014 — conf
POWER8 design methodology innovations for improving productivity and reducing power.
CICC
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
2013 J jnl
DB2 with BLU Acceleration: So Much More than Just a Column Store.
Proc. VLDB Endow.
Vijayshankar Raman, Gopi K. Attaluri, Ronald Barber, Naresh Chainani, David Kalmuk, Vincent KulandaiSamy, Jens Leenstra, Sam Lightstone, Shaorong Liu, Guy M. Lohman, Tim Malkemus, René Müller, Ippokratis Pandis, Berni Schiefer, David Sharpe, Richard Sidle, Adam J. Storm, Liping Zhang
2011 J jnl
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
IEEE J. Solid State Circuits
Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott A. Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban
2008 A* conf
Scan chain clustering for test power reduction.
DAC
Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding
2007 J jnl
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process.
J. Low Power Electron.
Joachim Fenkes, Tobias Gemmeke, Jens Leenstra
2007 J jnl
IBM POWER6 accelerators: VMX and DFU.
IBM J. Res. Dev.
Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough
2007 J jnl
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM J. Res. Dev.
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2007 A* conf
Scan Test Planning for Power Reduction.
DAC
Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
2006 A conf
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.
ITC
Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
2006 J jnl
The microarchitecture of the synergistic processor for a cell processor.
IEEE J. Solid State Circuits
Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2006 — conf
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
DATE Designers' Forum
Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller
2005 — conf
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
ESSCIRC
Nicolas Mäding, Jens Leenstra, Jürgen Pille, Rolf Sautter, Stefan Büttner, Sebastian Ehrenreich, W. Haller
2001 J jnl
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core.
IEEE J. Solid State Circuits
Jens Leenstra, Jürgen Pille, Antje Müller, Wolfram M. Sauer, Rolf Sautter, Dieter F. Wendel
2001 A conf
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
ITC
Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich
2000 J jnl
Custom circuit design as a driver of microprocessor performance.
IBM J. Res. Dev.
David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
1997 A* conf
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.
DAC
Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile
1991 A conf
Hierarchical Test Program Development for Scan Testable Circuits.
ITC
Jens Leenstra, Lambert Spaanenburg
1990 A conf
Hierarchical test assembly for macro based VLSI design.
ITC
Jens Leenstra, Lambert Spaanenburg
1989 C conf
Issues in the test of artificial neural networks.
ICCD
Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg
1989 J jnl
On structured gate forest VLSI design.
Microprocessing and Microprogramming
Gerhard Roos, Jens Leenstra, Thomas Schwederski, Lambert Spaanenburg, Bernd Höfflinger
1989 A conf
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems.
ITC
Jens Leenstra, Lambert Spaanenburg