Jeng-Liang Tsai

13 papers A 4C 1Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2006 — conf
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.
ASP-DAC
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
2006 C conf
Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method.
ISCAS
Pei-Yu Huang, Yu-Min Lee, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2006 J jnl
Temperature-Aware Placement for SOCs.
Proc. IEEE
Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar
2005 Misc conf
False Path and Clock Scheduling Based Yield-Aware Gate Sizing.
VLSI Design
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2005 — conf
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.
ASP-DAC
Jeng-Liang Tsai, Charlie Chung-Ping Chen
2005 A conf
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis.
ICCAD
Jeng-Liang Tsai, Lizheng Zhang
2005 J jnl
Yield-Driven, False-Path-Aware Clock Skew Scheduling.
IEEE Des. Test Comput.
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004 A conf
A yield improvement methodology using pre- and post-silicon statistical clock scheduling.
ICCAD
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja
2004 A conf
HiSIM: hierarchical interconnect-centric circuit simulator.
ICCAD
Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
2004 — conf
Sensitivity guided net weighting for placement driven synthesis.
ISPD
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2004 A conf
Thermal and Power Integrity Based Power/Ground Networks Optimization.
DATE
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
2004 J jnl
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen
2003 — conf
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.
ISPD
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen