Jen-Chieh Yeh - RankMe

37 papers A* 2A 4C 2Misc 5Journal 7Unranked 17

Year	Rank	Type	Title / Venue / Authors
2014	Misc	`conf`	3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system. ICASSP Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang
2014	J	`jnl`	DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
2014	—	`conf`	Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky
2014	J	`jnl`	Multi-core system performance prediction and analysis at the ESL. Int. J. Comput. Sci. Eng. Jen-Chieh Yeh, Chi-Hung Lin, Chun-Nan Liu
2013	—	`conf`	A Cycle Count Accurate TLM bus modeling approach. VLSI-DAT Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay
2013	—	`conf`	A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
2013	J	`jnl`	Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh
2013	—	`conf`	Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu
2012	—	`conf`	Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement. HPCC-ICESS Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang
2012	—	`conf`	Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL. ISQED Mao-Yin Wang, Jen-Chieh Yeh
2011	C	`conf`	Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. HPCC Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng
2011	A*	`conf`	PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh
2011	—	`conf`	System power analysis with DVFS on ESL virtual platform. SoCC Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen
2011	Misc	`conf`	System-level design exploration for 3-D stacked memory architectures. CODES+ISSS Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh
2010	A	`conf`	An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. DATE Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang
2010	—	`conf`	PAC duo system power estimation at ESL. ASP-DAC Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang
2009	C	`conf`	Full System Simulation and Verification Framework. IAS Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen, Kuen-Jong Lee, Yuan-Hua Chu, Jen-Chieh Yeh, Ying-Chuan Hsiao
2009	—	`conf`	System Performance Analyses on PAC Duo ESL Virtual Platform. IIH-MSP Zhe-Mao Hsu, I-Yao Chuang, Wen-Chien Su, Jen-Chieh Yeh, Jen-Kuei Yang, Shau-Yin Tseng
2008	J	`jnl`	A Systematic Approach to Memory Test Time Reduction. IEEE Des. Test Comput. Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo
2007	J	`jnl`	Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
2007	J	`jnl`	Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2007	Misc	`conf`	SDRAM Delay Fault Modeling and Performance Testing. VTS Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu
2006	A*	`conf`	A network security processor design based on an integrated SOC design and test platform. DAC Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006	A	`conf`	An Enhanced EDAC Methodology for Low Power PSRAM. ITC Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin
2006	—	`conf`	Fault-Pattern Oriented Defect Diagnosis for Flash Memory. MTDT Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu
2005	J	`jnl`	A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu
2005	—	`conf`	A systematic approach to reducing semiconductor memory test time in mass production. MTDT Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen
2005	Misc	`conf`	Flash Memory Built-In Self-Diagnosis with Test Mode Control. VTS Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin
2005	—	`conf`	Flash Memory Die Sort by a Sample Classification Method. Asian Test Symposium Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen
2004	—	`conf`	On Test and Diagnostics of Flash Memories. Asian Test Symposium Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu
2003	A	`conf`	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow
2002	—	`conf`	A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002	—	`conf`	A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
2002	A	`conf`	Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu
2002	—	`conf`	Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu
2002	Misc	`conf`	RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
2001	—	`conf`	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu