Jen-Chieh Liu

32 papers C 9Journal 19Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
A High Timing Resolution and Data Rate Pulse Generator for Automatic Test Equipment Applications.
IEEE Trans. Instrum. Meas.
Jen-Chieh Liu, Chi-Hua Chen, Cheng-En Wu
2025 J jnl
A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application.
Microelectron. J.
Jen-Chieh Liu, Jian-Sheng Li, Yanxun Chen, Yu-Lung Lo
2025 J jnl
A low-voltage and low-power PLL for Sub-GHz IoT applications.
Integr.
Jen-Chieh Liu, Rui-Cheng Ai
2025 J jnl
A programmable delay chain for the source-synchronous interface.
Integr.
Jen-Chieh Liu, Jun-Yu Chen, Wenqi Liu
2024 — conf
A Low-power PLL with a Standby Mode.
ISOCC
Yu-Chun Hsiao, Rui-Cheng Ai, Zhen-Jie Hong, Yu-Lung Lo, Jen-Chieh Liu
2024 — conf
A Programmable DLL-based Delay Chain.
ISOCC
Yu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, Jen-Chieh Liu
2023 J jnl
A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique.
Circuits Syst. Signal Process.
Hong-Yi Huang, Jen-Chieh Liu, Fu-Chien Tsai, Kun-Hua Lee, Kun-Yuan Chen
2021 J jnl
A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator.
IEEE Access
Jen-Chieh Liu, Yu-Ping Li
2018 J jnl
A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution.
IEEE Trans. Very Large Scale Integr. Syst.
Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee
2018 J jnl
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
2018 J jnl
Low supply voltage and multiphase all-digital crystal-less clock generator.
IET Circuits Devices Syst.
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
2018 J jnl
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs
Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou
2017 J jnl
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee
2016 J jnl
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.
IEICE Electron. Express
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
2016 J jnl
A Low Power Pulse Generator for Test Platform Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Jen-Chieh Liu, Pei-Ying Lee
2016 C conf
A chaotically injected timing technique for ring-based oscillators.
DDECS
Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
2016 J jnl
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.
IEICE Trans. Electron.
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
2015 C conf
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing.
DDECS
Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou
2014 J jnl
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes.
IEEE Trans. Circuits Syst. II Express Briefs
Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun
2014 C conf
A 64-MHz∼640-MHz 64-phase clock generator.
DDECS
Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
2014 C conf
A radio-controlled receiver for clocks/watches and alarm applications.
ISCAS
Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang
2012 J jnl
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator.
IEEE Trans. Circuits Syst. II Express Briefs
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang
2012 C conf
Auto-calibration techniques in built-in jitter measurement circuit.
DDECS
Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng
2011 J jnl
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler.
IEEE Trans. Circuits Syst. II Express Briefs
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu
2011 J jnl
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu
2011 C conf
All digital phase-locked loop using active inductor oscillator and novel locking algorithm.
ISCAS
Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo
2011 J jnl
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.
IEEE Trans. Very Large Scale Integr. Syst.
Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong
2010 — conf
A loading effect insensitive and high precision clock synchronization circuit.
ESSCIRC
Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen
2010 C conf
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.
DDECS
Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
2009 C conf
0.5V 160-MHz 260uW all digital phase-locked loop.
DDECS
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
2007 — conf
All-Digital PLL Using Pulse-Based DCO.
ICECS
Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng
2006 C conf
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.
ISCAS
Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu