Jeffrey Stuecheli

16 papers A* 6B 2Journal 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memory.
CoRR
Maccoy Merrell, Daniel Puckett, Gino Chacon, Jeffrey Stuecheli, Stavros Kalafatis, Paul V. Gratz
2021 A* conf
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
ISCA
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
2021 J jnl
IBM's POWER10 Processor.
IEEE Micro
William J. Starke, Brian W. Thompto, Jeffrey Stuecheli, José E. Moreira
2018 J jnl
IBM POWER9 memory architectures for optimized systems.
IBM J. Res. Dev.
William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella
2018 J jnl
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI.
IBM J. Res. Dev.
Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison
2015 J jnl
Advanced features in IBM POWER8 systems.
IBM J. Res. Dev.
Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block
2015 J jnl
CAPI: A Coherent Accelerator Processor Interface.
IBM J. Res. Dev.
Jeffrey Stuecheli, Bart Blaner, C. R. Johns, M. S. Siegel
2015 J jnl
The cache and memory subsystems of the IBM POWER8 processor.
IBM J. Res. Dev.
William J. Starke, Jeffrey Stuecheli, David Daly, J. S. Dodson, Florian Auernhammer, Patricia Sagmeister, Guy L. Guthrie, Charles F. Marino, M. S. Siegel, Bart Blaner
2013 A* conf
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.
ISCA
Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, José F. Martínez
2011 J jnl
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.
IEEE Micro
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
2011 B conf
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
PACT
Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John
2011 A* conf
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.
MICRO
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John
2010 A* conf
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.
HPCA
Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John
2010 A* conf
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.
MICRO
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John
2010 A* conf
The virtual write queue: coordinating DRAM and last-level cache policies.
ISCA
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John
2009 B conf
Bank-aware Dynamic Cache Partitioning for Multicore Architectures.
ICPP
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. John