Jeffrey L. Burns

21 papers A* 1A 4C 3Misc 2Journal 6Unranked 5

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	Panel discussions: "Cool chips for the next decade". COOL Chips Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash
2011	—	`conf`	Technology trends and implications on SoC design. SoCC Jeffrey L. Burns
2004	Misc	`conf`	Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
2004	J	`jnl`	Resonant clocking using distributed parasitic capacitance. IEEE J. Solid State Circuits Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown
2003	A	`conf`	A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
2003	A	`conf`	A semi-custom voltage-island technique and its application to high-speed serial links. ISLPED Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman
2003	—	`conf`	Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
2003	C	`conf`	Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. ICCD Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns
2003	A	`conf`	Efficient techniques for gate leakage estimation. ISLPED Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
2003	A	`conf`	Leakage and leakage sensitivity computation for combinational circuits. ISLPED Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
2002	J	`jnl`	A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE J. Solid State Circuits Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns
1999	Misc	`conf`	Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns
1998	J	`jnl`	A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
1998	C	`conf`	Area-oriented synthesis for pass-transistor logic. ICCD Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns
1998	J	`jnl`	C5M-a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeffrey L. Burns, Jack A. Feldman
1998	C	`conf`	Design methodology for a 1.0 GHz microprocessor. ICCD Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo
1998	J	`jnl`	Designing for a gigahertz [guTS integer processor]. IEEE Micro H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi
1997	—	`conf`	C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD Jeffrey L. Burns, Jack A. Feldman
1994	—	`conf`	The Effect of Wire Length Minimization on Yield. DFT Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns
1988	J	`jnl`	Techniques for multilayer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
1986	A*	`conf`	Chameleon: a new multi-layer channel router. DAC Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli