Jeffrey J. Cook

16 papers A* 1A 3B 3Misc 2Journal 3Unranked 3

Year	Rank	Type	Title / Venue / Authors
2018	A	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	B	`conf`	In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2018	—	`conf`	WRPN: Wide Reduced-Precision Networks. ICLR (Poster) Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2017	J	`jnl`	WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr
2017	J	`jnl`	WRPN: Wide Reduced-Precision Networks. CoRR Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2011	—	`—`	Scaling short read de novo DNA sequence assembly to gigabase genomes Jeffrey J. Cook
2009	A*	`conf`	Blueshift: Designing processors for timing speculation from the ground up. HPCA Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles
2009	B	`conf`	Characterizing and optimizing the memory footprint of de novo short read DNA sequence assembly. ISPASS Jeffrey J. Cook, Craig B. Zilles
2008	A	`conf`	A characterization of instruction-level error derating and its implications for error detection. DSN Jeffrey J. Cook, Craig B. Zilles
2007	J	`jnl`	A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. Microprocess. Microsystems Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter
2005	B	`conf`	Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. FPL Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb
2004	A	`conf`	A reconfigurable unit for a clustered programmable-reconfigurable processor. FPGA Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter
2003	—	`conf`	Mapping computation kernels to clustered programmable-reconfigurable processors. FPT Jeffrey J. Cook, Lee Baugh, Derek B. Gottlieb, Nicholas P. Carter
2002	—	`conf`	Clustered programmable-reconfigurable processors. FPT Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter
2002	Misc	`conf`	Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. FCCM Jeffrey J. Cook, Derek B. Gottlieb, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter
2002	Misc	`conf`	The Design of the Amalgam Reconfigurable Cluster. FCCM Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter