Jeffrey Goeders

29 papers A 5B 6C 1Misc 2Journal 6Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists. FPGA Eddie Rydell, Reilly McKendrick, Jeffrey Goeders
2025	C	`conf`	Open-Source Circuit Radiation Effects (OSCRE) Simulation Framework: Design and Applications. ISCAS Collin Lambert, Jacob Anderson, David Nichols, Parker Allred, Sharisse Poff, Jeffrey Goeders, Michael J. Wirthlin, Shiuh-Hua Wood Chiang
2025	J	`jnl`	Toward FPGA Intellectual Property Encryption from Netlist to Bitstream. ACM Trans. Reconfigurable Technol. Syst. Daniel Hutchings, Adam Taylor, Jeffrey Goeders
2024	B	`conf`	Techniques for Exploring Fine-Grained LUT and Routing Aging on a 28nm FPGA. FPL Hayden Cook, Jeffrey Goeders
2023	—	`conf`	Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison. ICFPT Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders
2023	B	`conf`	Improving the Reliability of FPGA CRO PUFs. FPL Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
2022	J	`jnl`	Approaches for FPGA Design Assurance. ACM Trans. Reconfigurable Technol. Syst. Eli Cahill, Brad L. Hutchings, Jeffrey Goeders
2022	—	`conf`	Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. FPT Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
2022	J	`jnl`	Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. ACM Trans. Reconfigurable Technol. Syst. Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings
2022	—	`conf`	Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering. FPT Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders
2021	A	`conf`	Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. DATE Benjamin James, Jeffrey Goeders
2020	J	`jnl`	Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton
2020	B	`conf`	Using Novel Configuration Techniques for Accelerated FPGA Aging. FPL Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings
2019	—	`conf`	An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	—	`conf`	Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. ReConFig Wesley Stirk, Jeffrey Goeders
2019	A	`conf`	On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	—	`conf`	Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs. FPT Matthew B. Ashcraft, Jeffrey Goeders
2018	B	`conf`	An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
2018	A	`conf`	Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
2018	Misc	`conf`	Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. FCCM Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings
2018	—	`conf`	Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs. FPT Matthew B. Ashcraft, Jeffrey Goeders
2018	—	`conf`	Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. IVSW Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings
2017	B	`conf`	Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton
2017	Misc	`conf`	Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. FCCM Jeffrey Goeders
2017	J	`jnl`	Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeffrey Goeders, Steven J. E. Wilton
2016	B	`conf`	Quantifying observability for in-system debug of high-level synthesis circuits. FPL Jeffrey Goeders, Steven J. E. Wilton
2015	—	`conf`	Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT Jeffrey Goeders, Steven J. E. Wilton
2014	J	`jnl`	VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2012	A	`conf`	The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson