Jeffrey A. Davis

30 papers A* 1A 2Misc 2Journal 12Unranked 13
YearRankTypeTitle / Venue / Authors
2021 J jnl
Multidimensional analysis of excitonic spectra of monolayers of tungsten disulphide: toward computer-aided identification of structural and environmental perturbations of 2D materials.
Mach. Learn. Sci. Technol.
Pavel V. Kolesnichenko, Qianhui Zhang, Changxi Zheng, Michael S. Fuhrer, Jeffrey A. Davis
2008 J jnl
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Vinita V. Deodhar, Jeffrey A. Davis
2007 J jnl
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation.
IEEE Trans. Very Large Scale Integr. Syst.
Hiroshi Yamamoto, Jeffrey A. Davis
2007 J jnl
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing.
IEEE Trans. Very Large Scale Integr. Syst.
Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis
2007 A conf
IntSim: A CAD tool for optimization of multilevel interconnect networks.
ICCAD
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
2006 — conf
A priori prediction of tightly clustered connections based on heuristic classification trees.
SLIP
Pranav Anbalagan, Jeffrey A. Davis
2006 Misc conf
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing.
VLSI Design
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
2005 — conf
Designing for signal integrity in wave-pipelined SOC global interconnects.
SoCC
Vinita V. Deodhar, Jeffrey A. Davis
2005 — conf
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing.
SoCC
Ajay Joshi, Jeffrey A. Davis
2005 J jnl
Optimization of throughput performance for low-power VLSI interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Vinita V. Deodhar, Jeffrey A. Davis
2005 — conf
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.
ISQED
Vinita V. Deodhar, Jeffrey A. Davis
2005 — conf
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing.
ACM Great Lakes Symposium on VLSI
Ajay Joshi, Jeffrey A. Davis
2005 J jnl
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst.
Ajay Joshi, Jeffrey A. Davis
2004 — conf
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).
SLIP
Ajay Joshi, Jeffrey A. Davis
2004 Misc conf
Maximum Multiplicity Distributions for Length Prediction Driven Placement.
VLSI Design
Pranav Anbalagan, Jeffrey A. Davis
2003 — conf
Computer Educational Datapath (CED): Basic Computer Design for K-12 Education.
ITCC
Alex Talpasanu, G. Milford, K. S. A. Miles, Jeffrey A. Davis
2003 — conf
Maximum multiplicity distributions (MMD).
SLIP
Pranav Anbalagan, Jeffrey A. Davis
2003 — conf
Voltage scaling and repeater insertion for high-throughput low-power interconnects.
ISCAS (5)
Vinita V. Deodhar, Jeffrey A. Davis
2002 A* conf
A physical model for the transient response of capacitively loaded distributed rlc interconnects.
DAC
Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
2002 J jnl
Interconnect opportunities for gigascale integration.
IBM J. Res. Dev.
James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
2001 J jnl
Impact of three-dimensional architectures on interconnects in gigascale integration.
IEEE Trans. Very Large Scale Integr. Syst.
James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
2001 J jnl
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).
IEEE Trans. Very Large Scale Integr. Syst.
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
2000 J jnl
A compact physical via blockage model.
IEEE Trans. Very Large Scale Integr. Syst.
Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
2000 — conf
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session).
SLIP
Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
2000 A conf
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion.
ISLPED
Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
2000 — conf
Prediction of interconnect fan-out distribution using Rent's rule.
SLIP
Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
2000 J jnl
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip.
IEEE Trans. Very Large Scale Integr. Syst.
Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
2000 J jnl
The fundamental limit on binary switching energy for terascale integration (TSI).
IEEE J. Solid State Circuits
James D. Meindl, Jeffrey A. Davis
2000 — conf
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures.
SLIP
James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
1998 — conf
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule.
CICC
Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl