Jeff Rearick - RankMe

46 papers A 29B 4Misc 6Journal 5Unranked 2

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges. ITC Hans Martin von Staudt, Jeff Rearick, Michael Laisne
2023	Misc	`conf`	Refreshing the JTAG Family. VTS Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg
2023	A	`conf`	Welcome Message ITC 2023. ITC Li-C. Wang, Jeff Rearick
2022	A	`conf`	IEEE P1687.1: Extending the Network Boundaries for Test. ITC Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo
2021	B	`conf`	Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim
2020	A	`conf`	Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices. ITC Hans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne
2020	B	`conf`	Linking Chip, Board, and System Test via Standards. ETS Michele Portolan, Jeff Rearick, Martin Keim
2020	A	`conf`	Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick
2019	Misc	`conf`	Innovative Practices on IEEE 1687.xyz. VTS Jeff Rearick, Alfred L. Crouch, Hans Martin von Staudt
2018	Misc	`conf`	Innovative practices on quality levels of A/MS devices. VTS Wim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick
2017	A	`conf`	Maximizing scan pin and bandwidth utilization with a scan routing fabric. ITC Yan Dong, Grady Giles, Guoliang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood
2017	J	`jnl`	Unleashing Fury: A New Paradigm for 3-D Design and Test. IEEE Des. Test Michael Alfano, Bryan Black, Jeff Rearick, Joseph Siegel, Michael Su, Julius Din
2017	A	`conf`	Use models for extending IEEE 1687 to analog test. ITC Peter Sarson, Jeff Rearick
2016	J	`jnl`	Streaming Access to ADCs and DACs for Mixed-Signal ATPG. IEEE Des. Test Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
2016	—	`conf`	Toward more efficient scan data bandwidth utilization on modern SOCs. SoCC Yan Dong, Grady Giles, Guoliang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood
2015	A	`conf`	Streaming fast access to ADCs and DACs for mixed-signal ATPG. ITC Stephen K. Sunter, Jean-Francois Cote, Jeff Rearick
2014	A	`conf`	Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns. ITC Sankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick
2013	B	`conf`	Magical thinking applied to test engineering reality (and vice versa). ETS Jeff Rearick
2012	B	`conf`	Re-using chip level DFT at board level. ETS Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson
2011	Misc	`conf`	Structural tests of slave clock gating in low-power flip-flop. VTS Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick
2010	Misc	`conf`	Selecting the most relevant structural Fmax for system Fmax correlation. VTS Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja
2010	A	`conf`	Vendor-agnostic native compression engine. ITC Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday
2009	A	`conf`	Cache-resident self-testing for I/O circuitry. ITC Sankar Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick
2009	A	`conf`	IEEE P1687 IJTAG a presentation of current technology. ITC Ken Posse, Al Crouch, Jeff Rearick
2009	J	`jnl`	Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2008	J	`jnl`	Overview of Debug Standardization Activities. IEEE Des. Test Comput. Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick
2008	A	`conf`	This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. ITC Jeff Rearick
2007	—	`conf`	Embedded Test Features for High-Speed Serial I/O. CICC Jeff Rearick
2007	J	`jnl`	Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. IEEE Des. Test Comput. Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick
2007	A	`conf`	Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2006	A	`conf`	A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. ITC Jeff Rearick, Aaron Volz
2006	A	`conf`	A Survey of Test Problems and Solutions. ITC Jeff Rearick
2006	A	`conf`	IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote
2005	A	`conf`	Calibrating clock stretch during AC scan testing. ITC Jeff Rearick, Richard Rodgers
2005	A	`conf`	IJTAG (internal JTAG): a step toward a DFT standard. ITC Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts
2004	A	`conf`	Integrating Boundary Scan into Multi-GHz I/O Circuitry. ITC Jeff Rearick, Sylvia Patterson, Krista Dorner
2003	A	`conf`	First IC Validation of IEEE Std. 1149.6. ITC Suzette Vandivier, Mark Wahl, Jeff Rearick
2003	Misc	`conf`	Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS Manish Sharma, Janak H. Patel, Jeff Rearick
2001	A	`conf`	Frequency detection-based boundary-scan testing of AC coupled nets. ITC Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick
2001	A	`conf`	Too much delay fault coverage is a bad thing. ITC Jeff Rearick
2000	A	`conf`	Deception by design: fooling ourselves with gate-level models. ITC Peter C. Maxwell, Jeff Rearick
1999	A	`conf`	Practical scan test generation and application for embedded FIFOs. ITC Jeff Rearick
1998	A	`conf`	Buying time for the stuck-at fault model. ITC Jeff Rearick
1998	A	`conf`	Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ITC Peter C. Maxwell, Jeff Rearick
1997	A	`conf`	The Case of Partial Scan. ITC Jeff Rearick
1993	A	`conf`	Fast and Accurate CMOS Bridging Fault Simulation. ITC Jeff Rearick, Janak H. Patel