Jeferson Santiago da Silva

14 papers A 3B 2C 1Misc 1Journal 6Unranked 1

Year	Rank	Type	Title / Venue / Authors
2021	A	`conf`	Design Principles for Packet Deparsers on FPGAs. FPGA Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
2021	J	`jnl`	Design Principles for Packet Deparsers on FPGAs. CoRR Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria
2020	C	`conf`	Bridging the Gap: FPGAs as Programmable Switches. HPSR Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2020	J	`jnl`	Bridging the Gap: FPGAs as Programmable Switches. CoRR Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2020	A	`conf`	Unleashing the Power of FPGAs as Programmable Switches. FPGA Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois
2019	Misc	`conf`	Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. FCCM Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2019	J	`jnl`	Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design. CoRR Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2018	B	`conf`	Extern Objects in P4: an ROHC Header Compression Scheme Case Study. NetSoft Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
2018	B	`conf`	One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. ICNP Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala
2018	J	`jnl`	One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. CoRR Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala
2018	A	`conf`	P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. FPGA Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2017	J	`jnl`	P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. CoRR Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois
2016	J	`jnl`	Extern Objects in P4: an ROHC Compression Case Study. CoRR Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois
2015	—	`conf`	Area-oriented iterative method for Design Space Exploration with High-Level Synthesis. LASCAS Jeferson Santiago da Silva, Sergio Bampi