Jean Durupt

13 papers B 3C 2Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2021 J jnl
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2020 — conf
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm
ISSCC
Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2019 B conf
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.
ETS
Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné
2018 — conf
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
ESSCIRC
Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet
2016 B conf
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.
ETS
Jean Durupt, Pascal Vivet, Juergen Schloeffel
2009 J jnl
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application.
IET Comput. Digit. Tech.
Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
2008 — conf
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.
NOCS
Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
2008 — conf
An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.
ESSCIRC
Carolynn Bernier, Frédéric Hameau, Gérard Billiot, Emeric de Foucauld, Stéphanie Robinet, Didier Lattard, Jean Durupt, Francois Dehmas, Laurent Ouvry, Pierre Vincent
2007 — conf
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip.
ISSCC
Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens
2007 — conf
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.
NOCS
Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach
2006 B conf
A DFT Architecture for Asynchronous Networks-on-Chip.
ETS
Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach
2006 C conf
Design-for-Test of Asynchronous Networks-on-Chip.
DDECS
Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand
1993 C conf
Experimental multiprocessor architecture dedicated for solving 3D PDEs.
PDP
J.-M. Libs, B. Siaud, Jean Durupt, Bernard Boutherin, Gilles Jacquemod, Michel Le Helley