Jean-Pierre David

91 papers A* 1A 4B 10C 11Misc 3Journal 33Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A Prototyping Framework for P4-Programmable Traffic Managers. RSP Karl La Grassa, André Béliveau, Mathieu Léonardon, Jean-Pierre David, Matthieu Arzel, Yvon Savaria
2025	J	`jnl`	Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches. IEEE Trans. Netw. Mostafa Elbediwy, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2025	J	`jnl`	Enhancing CuFP Library with Self-Alignment Technique. Comput. Fahimeh Hajizadeh, Tarek Ould-Bachir, Jean-Pierre David
2025	—	`conf`	Improved High-Radix Carry-Save Adders for Low-Latency Vector Reduction on Fpga. NewCAS Fahimeh Hajizadeh, Paul-André Bisson, Tarek Ould-Bachir, Jean-Pierre David
2025	J	`jnl`	P4Muse: Enabling Modular P4 Programming via Compiler-Managed Code Merging Without Syntax Modifications. IEEE Access Mohsen Rahmati, François-Raymond Boyer, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2024	—	`conf`	A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices. NewCAS Karim Kaced, Sebastien Genevey, Yvon Savaria, Jean-Pierre David
2024	J	`jnl`	DR-PIFO: A Dynamic Ranking Packet Scheduler Using a Push-In-First-Out Queue. IEEE Trans. Netw. Serv. Manag. Mostafa Elbediwy, Bill Pontikakis, Alireza Ghaffari, Jean-Pierre David, Yvon Savaria
2024	—	`conf`	MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks. MWSCAS Elisabeth Humblet, Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2024	J	`jnl`	Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. IEEE Access Nizar El Zarif, MohammadHossein AskariHemmat, Théo Dupuis, Jean-Pierre David, Yvon Savaria
2024	J	`jnl`	QGen: On the Ability to Generalize in Quantization Aware Training. CoRR MohammadHossein AskariHemmat, Ahmadreza Jeddi, Reyhane Askari Hemmat, Ivan Lazarevich, Alexander Hoffman, Sudhakar Sah, Ehsan Saboori, Yvon Savaria, Jean-Pierre David
2024	—	`conf`	Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits. MWSCAS Aymen-Alaeddine Zeghaida, Dinesh Daultani, J. M. Pierre Langlois, Jean-Pierre David
2024	A*	`conf`	Temporal Logic Explanations for Dynamic Decision Systems Using Anchors and Monte Carlo Tree Search (Abstract Reprint). AAAI Tzu-Yi Chiu, Jerome Le Ny, Jean-Pierre David
2023	J	`jnl`	A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access Mostafa Elbediwy, Bill Pontikakis, Jean-Pierre David, Yvon Savaria
2023	—	`conf`	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. ASP-DAC MohammadHossein AskariHemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. CoRR MohammadHossein AskariHemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David
2023	—	`conf`	Iterative pruning algorithm for efficient look-up table implementation of binary neural networks. NEWCAS Amirali Ebrahimi, Vineeth Narayan Pullu, J. M. Pierre Langlois, Jean-Pierre David
2023	—	`conf`	Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries. NEWCAS Dufour Jules, Yvon Savaria, Jean-Pierre David
2023	C	`conf`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	J	`jnl`	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David
2023	—	`conf`	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. NEWCAS Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2023	J	`jnl`	Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference. CoRR Théo Dupuis, Yoan Fournier, MohammadHossein AskariHemmat, Nizar El Zarif, François Leduc-Primeau, Jean-Pierre David, Yvon Savaria
2023	J	`jnl`	Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. Artif. Intell. Tzu-Yi Chiu, Jerome Le Ny, Jean-Pierre David
2023	J	`jnl`	Training DNNs Resilient to Adversarial and Random Bit-Flips by Learning Quantization Ranges. Trans. Mach. Learn. Res. Kamran Chitsaz, Gonçalo Mordido, Jean-Pierre David, François Leduc-Primeau
2022	—	`conf`	ASIP Accelerator for LUT-based Neural Networks Inference. NEWCAS Moussa Traore, J. M. Pierre Langlois, Jean-Pierre David
2022	C	`conf`	An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. ISCAS Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud
2022	—	`conf`	Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems. NEWCAS Jörg Ehmer, Bertrand Granado, Julien Denoulet, Yvon Savaria, Jean-Pierre David
2022	J	`jnl`	QReg: On Regularization Effects of Quantization. CoRR MohammadHossein AskariHemmat, Reyhane Askari Hemmat, Alexander Hoffman, Ivan Lazarevich, Ehsan Saboori, Olivier Mastropietro, Yvon Savaria, Jean-Pierre David
2021	J	`jnl`	Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Pierre David, Manuel J. Barragán
2021	C	`conf`	RISC-V Barrel Processor for Deep Neural Network Acceleration. ISCAS MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2020	J	`jnl`	Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Trans. Circuits Syst. Aref Trigui, Mohamed Ali, Sami Hached, Jean-Pierre David, Ahmed Chiheb Ammari, Yvon Savaria, Mohamad Sawan
2020	—	`ch.`	On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements. The Lognormality Principle Simon Pierre Boyogueno Bidias, Jean-Pierre David, Yvon Savaria, Réjean Plamondon
2020	J	`jnl`	POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. J. Signal Process. Syst. Ahmed M. Abdelsalam, Ahmed Elsheikh, Sivakumar Chidambaram, Jean-Pierre David, J. M. Pierre Langlois
2020	—	`conf`	PoET-BiN: Power Efficient Tiny Binary Neurons. MLSys Sivakumar Chidambaram, Pierre Langlois, Jean-Pierre David
2020	J	`jnl`	PoET-BiN: Power Efficient Tiny Binary Neurons. CoRR Sivakumar Chidambaram, J. M. Pierre Langlois, Jean-Pierre David
2020	Misc	`conf`	RISC-V Barrel Processor for Accelerator Control. FCCM MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2019	—	`conf`	A Low-Latency Reconfigurable Multistage Interconnection Network. CCECE Federico Montano, Tarek Ould-Bachir, Jean Mahseredjian, Jean-Pierre David
2019	A	`conf`	Binary Speech Features for Keyword Spotting Tasks. INTERSPEECH Alexandre Riviello, Jean-Pierre David
2019	C	`conf`	Bit-Slicing FPGA Accelerator for Quantized Neural Networks. ISCAS Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David
2019	—	`conf`	POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. DASIP Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois
2019	—	`conf`	U-Net Fixed-Point Quantization for Medical Image Segmentation. LABELS/HAL-MICCAI/CuRIOUS@MICCAI MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
2019	J	`jnl`	U-Net Fixed-Point Quantization for Medical Image Segmentation. CoRR MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David
2018	J	`jnl`	A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access Michel Gemieux, Meng Li, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
2018	—	`conf`	Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. DASIP Sivakumar Chidambaram, Alexandre Riviello, J. M. Pierre Langlois, Jean-Pierre David
2018	J	`jnl`	An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. Federico Montano, Tarek Ould-Bachir, Jean-Pierre David
2018	J	`jnl`	Automated Synthesis of Streaming Transfer Level Hardware Designs. ACM Trans. Reconfigurable Technol. Syst. Marc-André Daigneault, Jean-Pierre David
2018	—	`conf`	POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. DASIP Ahmed M. Abdelsalam, Ahmed Elsheikh, Jean-Pierre David, J. M. Pierre Langlois
2018	J	`jnl`	Ultra-low latency communication channels for FPGA-based HPC cluster. Integr. Roberto Sanchez Correa, Jean-Pierre David
2017	C	`conf`	A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. ISORC Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu
2017	—	`conf`	A data driven CGRA Overlay Architecture with embedded processors. NEWCAS Himan Khanzadi, Yvon Savaria, Jean-Pierre David
2017	J	`jnl`	Low latency and division free Gauss-Jordan solver in floating point arithmetic. J. Parallel Distributed Comput. Jean-Pierre David
2015	—	`conf`	BinaryConnect: Training Deep Neural Networks with binary weights during propagations. NIPS Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
2015	J	`jnl`	BinaryConnect: Training Deep Neural Networks with binary weights during propagations. CoRR Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
2015	—	`conf`	Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. IPDPS Workshops Marc-André Daigneault, Jean-Pierre David
2015	—	`conf`	Low latency solver for linear equation systems in floating point arithmetic. ReConFig Jean-Pierre David
2015	—	`conf`	Low precision arithmetic for deep learning. ICLR (Workshop) Matthieu Courbariaux, Yoshua Bengio, Jean-Pierre David
2015	—	`conf`	Mapping applications on two-level configurable hardware. AHS Himan Khanzadi, Yvon Savaria, Jean-Pierre David
2014	J	`jnl`	Fast description and synthesis of control-dominant circuits. Comput. Electr. Eng. Marc-André Daigneault, Jean-Pierre David
2013	J	`jnl`	A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. Math. Comput. Simul. Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
2013	A	`conf`	Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). FPGA Marc-André Daigneault, Jean-Pierre David
2013	Misc	`conf`	High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. FCCM Marc-André Daigneault, Jean-Pierre David
2013	—	`conf`	Max-hashing fragments for large data sets detection. ReConFig Jean-Pierre David
2013	J	`jnl`	Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. ACM Trans. Reconfigurable Technol. Syst. Tarek Ould-Bachir, Jean-Pierre David
2012	J	`jnl`	A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Trans. Ind. Electron. Hugo Fortin-Blanchette, Tarek Ould-Bachir, Jean-Pierre David
2012	—	`conf`	Effective floating-point calculation engines intended for the FPGA-based HIL simulation. ISIE Tarek Ould-Bachir, Christian Dufour, Jean Bélanger, Jean Mahseredjian, Jean-Pierre David
2012	B	`conf`	Raising the abstraction level of HDL for control-dominant applications. FPL Marc-André Daigneault, Jean-Pierre David
2012	—	`conf`	Synchronized-transfer-level design methodology applied to hardware matrix multiplication. ReConFig Marc-André Daigneault, Jean-Pierre David
2012	C	`conf`	Two-level configuration for FPGA: A new design methodology based on a computing fabric. ISCAS Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David
2011	J	`jnl`	A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. IEEE Trans. Instrum. Meas. Marc-André Daigneault, Jean-Pierre David
2011	J	`jnl`	Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Trans. Reconfigurable Technol. Syst. Etienne Bergeron, Louis-David Perron, Marc Feeley, Jean-Pierre David
2010	Misc	`conf`	Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. FCCM Tarek Ould Bachir, Jean-Pierre David
2010	A	`conf`	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). FPGA Marc-André Daigneault, Jean-Pierre David
2009	—	`conf`	A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. ReConFig Mathieu Allard, Patrick Grogan, Jean-Pierre David
2008	J	`jnl`	Analytical model for multi-junction solar cells prediction in space environment. Microelectron. Reliab. A. Gauffier, Jean-Pierre David, Olivier Gilard
2008	C	`conf`	Application Specific Instruction set processor specialized for block motion estimation. ICCD Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David
2008	B	`conf`	Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. CC Etienne Bergeron, Marc Feeley, Jean-Pierre David
2008	B	`conf`	Setting up On-Line Learning Experiments: The LearningLab Platform. ICALT Jean-Michel Adam, Anne Lejeune, Sandra Michelet, Jean-Pierre David, Christian Martel
2007	J	`jnl`	Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Trans. Computers Jean-Pierre David, Kassem Kalach, Nicolas Tittley
2006	B	`conf`	Comparing Educational Modeling Languages on a Case Study. ICALT Laurence Vignollet, Jean-Pierre David, Christine Ferraris, Christian Martel, Anne Lejeune
2006	B	`conf`	Expressing Learning Scenarios with Computer Independent Models. ICALT Emmanuelle Villiot-Leclercq, Jean-Pierre David, Anne Lejeune
2006	B	`conf`	Expressing Workshop Scenario with Computer Independent Model. ICALT Jean-Pierre David, Anne Lejeune, Emmanuelle Villiot-Leclercq
2006	B	`conf`	LDL: An Alternative EML. ICALT Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune
2006	B	`conf`	Modeling Collaborative Learning Activities on e-Learning Platforms. ICALT Christian Martel, Laurence Vignollet, Christine Ferraris, Jean-Pierre David, Anne Lejeune
2005	C	`conf`	High Level Synthesis for Data-Driven Applications. IEEE International Workshop on Rapid System Prototyping Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David
2004	—	`conf`	A Step towards Intelligent Translation from High-Level Design to RTL. IWSOC Jean-Pierre David, Etienne Bergeron
2004	C	`conf`	An Intermediate Level HDL for System Level Design. FDL Jean-Pierre David, Etienne Bergeron
2002	B	`conf`	A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. FPL Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat
2002	B	`conf`	An FPGA Implementation of the Linear Cryptanalysis. FPL François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
2001	A	`conf`	Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. IPDPS Jean-Pierre David, Tony Postiau, Paul Fisette, Jean-Didier Legat
1998	C	`conf`	A Data-Flow Oriented Co-Design for Reconfigurable Systems. International Workshop on Rapid System Prototyping Jean-Pierre David, Jean-Didier Legat
1996	—	`conf`	Hypermedia Exercises Prototyping and Modelising. CALISCE Jean-Pierre David, André Cogne, Annick Dutel
1994	J	`jnl`	Software environments for computer aided education. ACM SIGCSE Bull. Viviane Guéraud, Jean-Michel Cagnat, Jean-Pierre David, Jean-Philippe Pernin