Jean-Olivier Plouchart

46 papers A* 1A 3Journal 17Unranked 25

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency. IEEE J. Solid State Circuits Wooram Lee, Caglar Ozdag, Jean-Olivier Plouchart, Alberto Valdes-Garcia, Bodhisatwa Sadhu
2023	—	`conf`	Cryogenic CMOS: design considerations for future quantum computing systems. CICC Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
2022	J	`jnl`	A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Arun Paidimarri, Duixian Liu, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
2022	—	`conf`	A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. ISSCC Bodhisatwa Sadhu, Arun Paidimarri, Wooram Lee, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Jean-Olivier Plouchart, Xiaoxiong Gu, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
2020	J	`jnl`	A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
2018	J	`jnl`	Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C. IEEE J. Solid State Circuits Wooram Lee, Jean-Olivier Plouchart, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Scott K. Reynolds, Emre Apaydin, Alberto Valdes-Garcia
2018	—	`conf`	Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman
2017	—	`conf`	An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI. MWSCAS Jen-Chieh Hsueh, Vanessa H.-C. Chen, Jean-Olivier Plouchart
2015	A	`conf`	Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information. ICCAD Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia
2014	J	`jnl`	Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman
2014	J	`jnl`	Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
2013	J	`jnl`	Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	—	`conf`	Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
2011	—	`conf`	A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI. CICC Mihai A. T. Sanduleanu, Scott K. Reynolds, Jean-Olivier Plouchart
2011	J	`jnl`	Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi
2010	—	`conf`	An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi
2009	—	`conf`	An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS. ISSCC Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Jean-Olivier Plouchart, Mahender Kumar, Woo-Hyeong Lee, Ken Rim
2009	—	`conf`	Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
2008	—	`conf`	A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
2008	—	`conf`	Wideband mmWave CML static divider in 65nm SOI CMOS technology. CICC Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart
2007	—	`conf`	A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS. ISSCC Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Weipeng Li, Daihyun Lim, Robert Trzcinski, Mahender Kumar, Christine Norris, David Ahlgren
2007	—	`conf`	A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. ISQED Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski
2007	—	`conf`	Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS. ISSCC Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik D. Kim, Robert Trzcinski, Duane S. Boning
2007	A*	`conf`	Statistical Framework for Technology-Model-Product Co-Design and Convergence. DAC Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski
2006	—	`conf`	CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement. CICC Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren
2006	—	`conf`	Performance Variations of a 66GHz Static CML Divider in 90nm CMOS. ISSCC Jean-Olivier Plouchart, Jonghae Kim, Victor Karam, Robert Trzcinski, Jeff Gross
2004	J	`jnl`	A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology. IEEE J. Solid State Circuits Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
2004	J	`jnl`	A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology. IEEE J. Solid State Circuits Neric H. W. Fong, Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Garry Tarr
2004	—	`conf`	Design and manufacturability aspect of SOI CMOS RFICs. CICC Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer
2003	A	`conf`	A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology. ISLPED Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner
2003	—	`conf`	A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology. ESSCIRC Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
2003	—	`conf`	A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology. CICC Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
2003	A	`conf`	A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. ISLPED Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner
2003	J	`jnl`	Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. IBM J. Res. Dev. Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier
2003	J	`jnl`	Design of wide-band CMOS VCO for multiband wireless LAN applications. IEEE J. Solid State Circuits Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, N. Garry Tarr
2003	J	`jnl`	Frequency-independent equivalent-circuit model for on-chip spiral inductors. IEEE J. Solid State Circuits Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu
2002	—	`conf`	A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS. CICC Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Gerry Tarr
2002	—	`conf`	Frequency-independent equivalent circuit model for on-chip spiral inductors. CICC Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu
2000	J	`jnl`	Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart
1999	—	`conf`	A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. CICC Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer