Jean-Michel Portal

159 papers A 17B 2C 14Misc 1Journal 49Unranked 76

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Forward-only learning in memristor arrays with month-scale stability. CoRR Adrien Renaudineau, Mamadou Hawa Diallo, Théo Dupuis, Bastien Imbert, Mohammed Akib Iftakher, Kamel-Eddine Harabi, Clément Turck, Tifenn Hirtzlin, Djohan Bonnet, Franck Melul, Jorge-Daniel Aguirre-Morales, Elisa Vianello, Marc Bocquet, Jean-Michel Portal, Damien Querlioz
2025	—	`conf`	Dual-Mode 16kb Memory: Transforming a Ferroelectric Capacitor Bitcell into Resistive Filamentary Memory. IMW Tarcisius Januel, Olivier Billoint, Laurent Grenouillet, S. Martin, Jean-Michel Portal, Elisa Vianello
2025	J	`jnl`	Unsupervised local learning based on voltage-dependent synaptic plasticity for resistive and ferroelectric synapses. CoRR Nikhil Garg, Ismael Balafrej, Joao Henrique Quintino Palhares, Laura Bégon-Lours, Davide Florini, Donato Francesco Falcone, Tommaso Stecconi, Valeria Bragaglia, Bert Jan Offrein, Jean-Michel Portal, Damien Querlioz, Yann Beilliard, Dominique Drouin, Fabien Alibart
2024	J	`jnl`	The Logarithmic Memristor-Based Bayesian Machine. CoRR Clement Türck, Kamel-Eddine Harabi, Adrien Pontlevy, Théo Ballet, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean-Michel Portal, Damien Querlioz
2024	—	`conf`	Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits. ICONS Nikhil Garg, Davide Florini, Patrick Dufour, Eloir Muhr, Mathieu-Coumba Faye, Marc Bocquet, Damien Querlioz, Yann Beilliard, Dominique Drouin, Fabien Alibart, Jean-Michel Portal
2024	J	`jnl`	Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits. CoRR Nikhil Garg, Davide Florini, Patrick Dufour, Eloi Muhr, Mathieu-Coumba Faye, Marc Bocquet, Damien Querlioz, Yann Beilliard, Dominique Drouin, Fabien Alibart, Jean-Michel Portal
2023	—	`conf`	1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation. MIXDES Joel Minguet Lopez, Manon Dampfhoffer, Tifenn Hirtzlin, Lucas Reganaz, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Thomas Magis, Catherine Carabasse, Niccolo Castellani, Valentina Meli, Elisa Vianello, Damien Deleruyelle, Jean-Michel Portal, Gabriel Molas, François Andrieu
2023	—	`conf`	A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. ASP-DAC Kamel-Eddine Harabi, Clement Türck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal
2023	J	`jnl`	A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. CoRR Kamel-Eddine Harabi, Clement Türck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal
2023	A	`conf`	Binary ReRAM-based BNN first-layer implementation. DATE Mona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean-Michel Portal
2023	A	`conf`	Energy-Efficient Bayesian Inference Using Near-Memory Computation with Memristors. DATE Clement Türck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean-Michel Portal, Damien Querlioz
2023	J	`jnl`	Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell. CoRR Fadi Jebali, Atreya Majumdar, Clement Türck, Kamel-Eddine Harabi, Mathieu-Coumba Faye, Eloi Muhr, Jean-Pierre Walder, Oleksandr Bilousov, Amadeo Michaud, Elisa Vianello, Tifenn Hirtzlin, François Andrieu, Marc Bocquet, Stéphane Collin, Damien Querlioz, Jean-Michel Portal
2022	—	`conf`	1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing. IMW Joel Minguet Lopez, François Rummens, Lucas Reganaz, A. Heraud, Tifenn Hirtzlin, Laurent Grenouillet, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Niccolo Castellani, Valentina Meli, S. Martin, Thomas Magis, Elisa Vianello, C. Sabbione, Damien Deleruyelle, Marc Bocquet, Jean-Michel Portal, Gabriel Molas, François Andrieu
2022	J	`jnl`	Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. Adv. Intell. Syst. Eduardo Esmanhotto, Tifenn Hirtzlin, Djohan Bonnet, Niccolo Castellani, Jean-Michel Portal, Damien Querlioz, Elisa Vianello
2022	J	`jnl`	Experimental Demonstration of Multilevel Resistive Random Access Memory Programming for up to Two Months Stable Neural Networks Inference Accuracy. Adv. Intell. Syst. Eduardo Esmanhotto, Tifenn Hirtzlin, Djohan Bonnet, Niccolo Castellani, Jean-Michel Portal, Damien Querlioz, Elisa Vianello
2022	—	`conf`	Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. IRPS Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-François Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello
2022	J	`jnl`	Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations. CoRR Eduardo Esmanhotto, Tifenn Hirtzlin, Niccolo Castellani, S. Martin, Bastien Giraud, François Andrieu, Jean-Francois Nodin, Damien Querlioz, Jean-Michel Portal, Elisa Vianello
2022	J	`jnl`	Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential. CoRR Nikhil Garg, Ismael Balafrej, Terrence C. Stewart, Jean-Michel Portal, Marc Bocquet, Damien Querlioz, Dominique Drouin, Jean Rouat, Yann Beilliard, Fabien Alibart
2021	J	`jnl`	A Memristor-Based Bayesian Machine. CoRR Kamel-Eddine Harabi, Tifenn Hirtzlin, Clement Türck, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Jean-Michel Portal, Marc Bocquet, Damien Querlioz
2021	—	`conf`	A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. VLSI-SoC (Selected Papers) J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal
2021	C	`conf`	A Self-referenced and regulated sensing solution for PCM with OTS selector. VLSI-SoC J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Pierre Walder, Jean-Michel Portal
2021	—	`conf`	CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks. MWSCAS Fadi Jebali, Atreya Majumdar, Axel Laborieux, Tifenn Hirtzlin, Elisa Vianello, Jean-Pierre Walder, Marc Bocquet, Damien Querlioz, Jean-Michel Portal
2021	—	`conf`	Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization. IRPS Joel Minguet Lopez, Lucas Hudeley, Laurent Grenouillet, Diego Alfaro Robayo, Jury Sandrini, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Damien Deleruyelle, Niccolo Castellani, Marc Bocquet, Jean-Michel Portal, Etienne Nowak, Gabriel Molas
2021	—	`conf`	Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays. IMW Joel Minguet Lopez, Niccolo Castellani, Laurent Grenouillet, Lucas Reganaz, Gabriele Navarro, Mathieu Bernard, Catherine Carabasse, Thomas Magis, Damien Deleruyelle, Marc Bocquet, Jean-Michel Portal, Etienne Nowak, Gabriel Molas
2021	J	`jnl`	Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse. IEEE Trans. Circuits Syst. I Regul. Pap. Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2021	—	`conf`	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSCIRC Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal
2021	—	`conf`	Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges. ESSDERC Mona Ezzadeen, Atreya Majumdar, Marc Bocquet, Bastien Giraud, Jean-Philippe Noël, François Andrieu, Damien Querlioz, Jean-Michel Portal
2021	J	`jnl`	Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks. CoRR Atreya Majumdar, Marc Bocquet, Tifenn Hirtzlin, Axel Laborieux, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2021	A	`conf`	Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal
2020	A	`conf`	Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud
2020	—	`conf`	Embracing the Unreliability of Memory Devices for Neuromorphic Computing. IRPS Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	J	`jnl`	Embracing the Unreliability of Memory Devices for Neuromorphic Computing. CoRR Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	J	`jnl`	Implementation of Ternary Weights with Resistive RAM Using a Single Sense Operation per Synapse. CoRR Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	A	`conf`	In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. DATE Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	J	`jnl`	In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications. CoRR Bogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	—	`conf`	Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. AICAS Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Liza Herrera Diez, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	J	`jnl`	Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse. CoRR Axel Laborieux, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Liza Herrera Diez, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2020	J	`jnl`	Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications. CoRR Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu
2020	J	`jnl`	Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
2019	J	`jnl`	Digital Biologically Plausible Implementation of Binarized Neural Networks with Differential Hafnium Oxide Resistive Memory Arrays. CoRR Tifenn Hirtzlin, Marc Bocquet, Bogdan Penkovsky, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2019	C	`conf`	Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM. IOLTS Mounia Kharbouche-Harrari, Romain Wacquez, Gregory di Pendina, Jean-Max Dutertre, Jérémy Postel-Pellerin, Driss Aboulkassimi, Jean-Michel Portal
2019	—	`conf`	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. NANOARCH Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein, Nicolas Locatelli, Adrien F. Vincent, Marc Bocquet, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. CoRR Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein, Nicolas Locatelli, Adrien F. Vincent, Marc Bocquet, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks. CoRR Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2019	C	`conf`	Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis. ISCAS Mounia Kharbouche-Harrari, Gregory di Pendina, Romain Wacquez, Bernard Dieny, Driss Aboulkassimi, Jérémy Postel-Pellerin, Jean-Michel Portal
2019	—	`conf`	Memory-Centric Neuromorphic Computing With Nanodevices. BioCAS Damien Querlioz, Julie Grollier, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Marc Bocquet, Jean-Michel Portal, Miguel Romera, Philippe Talatchian
2019	—	`conf`	Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks. AICAS Tifenn Hirtzlin, Marc Bocquet, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks. CoRR Tifenn Hirtzlin, Marc Bocquet, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	Stochastic Computing for Hardware Implementation of Binarized Neural Networks. IEEE Access Tifenn Hirtzlin, Bogdan Penkovsky, Marc Bocquet, Jacques-Olivier Klein, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	Stochastic Computing for Hardware Implementation of Binarized Neural Networks. CoRR Tifenn Hirtzlin, Bogdan Penkovsky, Marc Bocquet, Jacques-Olivier Klein, Jean-Michel Portal, Damien Querlioz
2019	J	`jnl`	Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. IEEE Trans. Circuits Syst. II Express Briefs Mouhamad Alayan, Eloi Muhr, Alexandre Levisse, Marc Bocquet, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, Jean-Michel Portal
2018	J	`jnl`	An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories. J. Low Power Electron. Steve Ngueya W., Jean-Michel Portal, Hassen Aziza, Julien Mellier, Stephane Ricard
2018	C	`conf`	Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. IOLTS Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal
2018	—	`conf`	RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2018	C	`conf`	Reliable ReRAM-based Logic Operations for Computing in Memory. VLSI-SoC Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel
2018	C	`conf`	Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS Elena-Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat
2018	—	`conf`	Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip. IRPS Thibault Kempf, Vincenzo Della Marca, L. Baron, F. Maugain, Francesco La Rosa, Stephan Niel, Arnaud Régnier, Jean-Michel Portal, Pascal Masson
2017	J	`jnl`	A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps. J. Low Power Electron. Steve Ngueya W., Jean-Michel Portal, Hassen Aziza, Julien Mellier, Stephane Ricard
2017	—	`conf`	An Ultra-Low Power and High Speed Single Ended Sense Amplifier for Non-Volatile Memories. NGCAS Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza
2017	—	`conf`	Architecture, design and technology guidelines for crosspoint memories. NANOARCH Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2017	C	`conf`	Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
2017	—	`conf`	High density emerging resistive memories: What are the limits? LASCAS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2017	—	`conf`	High voltage recycling scheme to improve power consumption of regulated charge pumps. PATMOS Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza
2017	—	`conf`	Power efficiency optimization of charge pumps in embedded low voltage NOR flash memory. NORCAS Steve Ngueya W., Julien Mellier, Stephane Ricard, Jean-Michel Portal, Hassen Aziza
2017	C	`conf`	Thermal laser attack and high temperature heating on HfO2-based OxRAM cells. IOLTS Alexis Krakovinsky, Marc Bocquet, Romain Wacquez, Jean Coignus, Jean-Michel Portal
2016	—	`conf`	Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal
2016	—	`conf`	Multilevel operation in oxide based resistive RAM with SET voltage modulation. DTIS Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet
2016	J	`jnl`	Optimization of a Particles Detection Chain Based on a VCO Structure. J. Electron. Test. Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal
2016	J	`jnl`	Resistive RAM variability monitoring using a ring oscillator based test chip. Microelectron. Reliab. Hassen Aziza, Jean-Michel Portal
2015	—	`conf`	Dynamic current reduction of CMOS digital circuits through design and process optimization. PATMOS Jordan Innocenti, Loïc Welter, Nicolas Borrel, Franck Julien, Jean-Michel Portal, Jacques Sonzogni, Laurent Lopez, Pascal Masson, Stephan Niel, Philippe Dreux, Julia Castellan
2015	J	`jnl`	Improvement of MOSFET matching characterization with calibrated multiplexed test structure. Microelectron. Reliab. Loic Welter, J. L. Scotto di Quaquero, Philippe Dreux, Laurent Lopez, Hassen Aziza, Jean-Michel Portal
2015	—	`conf`	Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment. LATS Karine Coulié-Castellani, Wenceslas Rahajandraibe, Hassen Aziza, Jean-Michel Portal, Gilles Micolau
2015	—	`conf`	Layout optimizations to decrease internal power and area in digital CMOS standard cells. MIPRO Jordan Innocenti, Franck Julien, Jean-Michel Portal, Laurent Lopez, Q. Hubert, Pascal Masson, Jacques Sonzogni, Stephan Niel, Arnaud Régnier
2015	—	`conf`	Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver. LATS Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal
2015	—	`conf`	SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
2014	—	`conf`	Accurate multiplexed test structure for threshold voltage matching evaluation. DTIS Loic Welter, Philippe Dreux, Jordan Innocenti, Hassen Aziza, Jean-Michel Portal
2014	C	`conf`	An innovative standard cells remapping method for in-circuit critical parameters monitoring. IOLTS Loic Welter, Philippe Dreux, Hassen Aziza, Jean-Michel Portal
2014	J	`jnl`	Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014	—	`conf`	Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology. MWSCAS Jordan Innocenti, Loic Welter, Franck Julien, Laurent Lopez, Jacques Sonzogni, Stephan Niel, Arnaud Régnier, Emmanuel Paire, Karen Labory, Eric Denis, Jean-Michel Portal, Pascal Masson
2014	—	`conf`	Improvement of a VCO concept for low energy particule detection and recognition. LATW Karine Coulié-Castellani, Wenceslas Rahajandraibe, Gilles Micolau, Hassen Aziza, Jean-Michel Portal
2014	J	`jnl`	Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation. J. Low Power Electron. Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Coulié-Castellani, Jean-Michel Portal
2014	—	`conf`	OxRAM-based non volatile flip-flop in 28nm FDSOI. NEWCAS Nenad Jovanovic, Olivier Thomas, Elisa Vianello, Jean-Michel Portal, Bosko Nikolic, Lirida A. B. Naviner
2014	—	`conf`	Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability. DFT Hassen Aziza, Haithem Ayari, Santhosh Onkaraiah, Jean-Michel Portal, Mathieu Moreau, Marc Bocquet
2014	—	`conf`	Printed complementary organic thin film transistors based decoder for ferroelectric memory. ESSCIRC Abdelali El Amraoui, Marc Bocquet, F. Barros, Jean-Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih, Vincent Fischer, Romain Coppard, R. Gwoziecky
2014	J	`jnl`	RRAM-based FPGA for "Normally Off, Instantly On" applications. J. Parallel Distributed Comput. Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, Marc Bocquet
2014	A	`conf`	Resistive memories: Which applications? DATE Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet
2014	J	`jnl`	Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. IEEE Trans. Circuits Syst. I Regul. Pap. Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
2013	—	`conf`	A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. ICICDT Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller
2013	C	`conf`	A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array. ISCAS Santhosh Onkaraiah, Ogun Turkyilmaz, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller
2013	J	`jnl`	A novel test structure for OxRRAM process variability evaluation. Microelectron. Reliab. Hassen Aziza, Marc Bocquet, Jean-Michel Portal, Mathieu Moreau, Christophe Muller
2013	—	`conf`	Analytical study of complementary memristive synchronous logic gates. NANOARCH Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
2013	—	`conf`	Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver. LATW Wenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal
2013	—	`conf`	DCG-FGT transistor: Retention study of Floating Gate charge. MWSCAS Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour
2013	C	`conf`	Embedded high-precision frequency-based capacitor measurement system. IOLTS Loic Welter, Philippe Dreux, Jean-Michel Portal, Hassen Aziza
2013	—	`conf`	Low-cost auto-calibration of passive polyphase filter in image reject receiver. ICECS Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal, Jamel Nebhen, Hervé Barthélemy
2013	Misc	`conf`	On the investigation of built-in tuning of RF receivers using on-chip polyphase filters. VTS Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal
2013	—	`conf`	SPICE level analysis of Single Event Effects in an OxRRAM cell. LATW Karine Castellani-Coulié, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Wenceslas Rahajandraibe, Christophe Muller
2013	—	`conf`	Single-ended sense amplifier robustness evaluation for OxRRAM technology. IDT Hassen Aziza, Marc Bocquet, Mathieu Moreau, Jean-Michel Portal
2013	—	`conf`	Synchronous full-adder based on complementary resistive switching memory cells. NEWCAS Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012	—	`conf`	A new adustable Schmitt Trigger based on Dual Control Gate-Floating Gate Transistor (DCG-FGT). MWSCAS Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour
2012	—	`conf`	Bipolar ReRAM Based non-volatile flip-flops for low-power architectures. NEWCAS Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Hraziia, Costin Anghel, Amara Amara
2012	—	`conf`	Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring. LATW Fayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal
2012	—	`conf`	Crossbar architecture based on 2R complementary resistive switching memory cell. NANOARCH Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012	J	`jnl`	Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. J. Low Power Electron. Guillaume Just, Vincenzo Della Marca, Arnaud Régnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, Jean-Michel Portal, Pascal Masson
2012	—	`conf`	Investigation of a CMOS oscillator concept for particle detection and diagnosis. LATW Karine Castellani-Coulié, Hassen Aziza, Wenceslas Rahajandraibe, Gilles Micolau, Jean-Michel Portal
2012	J	`jnl`	Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications. J. Low Power Electron. Jean-Michel Portal, Marc Bocquet, Damien Deleruyelle, Christophe Muller
2012	J	`jnl`	Optimization of SEU Simulations for SRAM Cells Reliability under Radiation. J. Electron. Test. Karine Castellani-Coulié, Hassen Aziza, Gilles Micolau, Jean-Michel Portal
2012	—	`conf`	PSP based DCG-FGT transistor Model: Full characterization procedure. ISCIT Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour
2012	—	`conf`	RRAM-based FPGA for "normally off, instantly on" applications. NANOARCH Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, Marc Bocquet
2012	—	`conf`	SITARe: A simulation tool for analysis and diagnosis of radiation effects. LATW Gilles Micolau, Karine Castellani-Coulié, Hassen Aziza, Jean-Michel Portal
2011	—	`conf`	Analysis of SEU parameters for the study of SRAM cells reliability under radiation. LATW Karine Castellani-Coulié, Jean-Michel Portal, Gilles Micolau, Hassen Aziza
2011	J	`jnl`	Back-end soft and hard defect monitoring using a single test chip. Microelectron. Reliab. Fabrice Rigaud, Jean-Michel Portal, Hassen Aziza, Didier Née, Julien Vast, Fabrice Argoud, Bertrand Borot
2011	—	`conf`	Bipolar OxRRAM memory array reliability evaluation based on fault injection. IDT Hassen Aziza, Marc Bocquet, Jean-Michel Portal, Christophe Muller
2011	—	`conf`	Design challenges for prototypical and emerging memory concepts relying on resistance switching. CICC Christophe Muller, Damien Deleruyelle, Olivier Ginez, Jean-Michel Portal, Marc Bocquet
2011	—	`conf`	Impact of SEU configurations on a SRAM cell response at circuit level. LATW Gilles Micolau, Hassen Aziza, Karine Castellani-Coulié, Jean-Michel Portal
2011	J	`jnl`	Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress. Microelectron. Reliab. Y. Joly, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Jean-Luc Ogier, Y. Bert, Franck Julien, Pascal Fornara
2011	—	`conf`	PSP based DCG-FGT transistor model including characterization procedure. ICECS Abderrezak Marzaki, V. Bidal, Romain Laffont, Wenceslas Rahajandraibe, Jean-Michel Portal, Rachid Bouchakour
2011	C	`conf`	Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area. ISCAS Y. Joly, L. Truphemus, Laurent Lopez, Jean-Michel Portal, Hassen Aziza, Franck Julien, Pascal Fornara
2011	—	`conf`	Using OxRRAM memories for improving communications of reconfigurable FPGA architectures. NANOARCH Santhosh Onkaraiah, Pierre-Emmanuel Gaillardon, Marina Reyboz, Fabien Clermidy, Jean-Michel Portal, Marc Bocquet, Christophe Muller
2009	C	`conf`	An on-line testing scheme for repairing purposes in Flash memories. DDECS Olivier Ginez, Jean-Michel Portal, Hassen Aziza
2009	—	`conf`	Definition of an innovative filling structure for digital blocks : the DFM filler cell. ICECS Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal
2009	B	`conf`	Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. ETS Olivier Ginez, Jean-Michel Portal, Christophe Muller
2008	A	`conf`	A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. ITC Olivier Ginez, Jean-Michel Portal, Hassen Aziza
2008	J	`jnl`	A Novel Low Power Oriented Design Methodology for Analog Blocks. J. Low Power Electron. Hassen Aziza, Emmanuel Bergeret, Jean-Michel Portal, Olivier Ginez
2008	—	`conf`	Metal filling impact on standard cells: definition of the metal fill corner concept. SBCCI Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal
2008	—	`conf`	Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ISQED Manuel Sellier, Jean-Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy
2007	J	`jnl`	A New Embedded Measurement Structure for eDRAM Capacitor CoRR Laurent Lopez, Jean-Michel Portal, Didier Née
2006	C	`conf`	MM11 based flash memory cell model including characterization procedure. ISCAS B. Saillet, Arnaud Régnier, Jean-Michel Portal, B. Delsuc, Romain Laffont, Pascal Masson, Rachid Bouchakour
2005	A	`conf`	A New Embedded Measurement Structure for eDRAM Capacitor. DATE Laurent Lopez, Jean-Michel Portal, Didier Née
2005	J	`jnl`	EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement. J. Electron. Test. Jean-Michel Portal, Hassen Aziza, Didier Née
2005	—	`conf`	Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. DFT B. Saillet, Jean-Michel Portal, Didier Née
2004	A	`conf`	A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. DATE Sandrine Bernardini, Jean-Michel Portal, Pascal Masson
2004	—	`conf`	Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. ISCAS (2) Anna Labbé, Annie Pérez, Jean-Michel Portal
2003	A	`conf`	EEPROM Memory: Threshold Voltage Built In Self Diagnosis. ITC Jean-Michel Portal, Hassen Aziza, Didier Née
2003	A	`conf`	Infrastructure IP for Back-End Yield Improvement. ITC L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot
2002	—	`conf`	An Automated Design Methodology for EEPROM Cell (ADE). MTDT Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née
2002	A	`conf`	An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell. ITC Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née
2002	—	`conf`	Floating-gate EEPROM cell model based on MOS model 9. ISCAS (3) Jean-Michel Portal, L. Forli, Didier Née
2002	—	`conf`	Floating-gate EEPROM cell: threshold voltage sensibility to geometry. ISCAS (1) Jean-Michel Portal, L. Forli, Didier Née
2001	J	`jnl`	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2001	—	`conf`	Analyzing bridging faults impact on EEPROM cell array. ETW Jean-Michel Portal, Annie Pérez
2001	A	`conf`	IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	J	`jnl`	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	—	`conf`	Analyzing the test generation problem for an application-oriented test of FPGAs. ETW Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Test Configuration Generation for FPGA Logic Cells. LATW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	J	`jnl`	Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	—	`conf`	Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	J	`jnl`	SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	—	`conf`	Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	Novel Technique for Testing FPGAs. DATE Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
1998	A	`conf`	RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	B	`conf`	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	SRAM-based FPGA's: testing the LUT/RAM modules. ITC Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	J	`jnl`	Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	—	`conf`	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian