Jean-Marc Daveau

36 papers A 1B 2C 8Misc 1Journal 8Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive Standards. LATS Esther Goudet, Fabio Sureau, Manan Kaila, Rémi Germe, Luis Peña Treviño, Jean-Marc Daveau, Lirida Naviner, Philippe Roche
2025	C	`conf`	Comparative Study of Safety and Security-Protected AES Designs. DDECS Daniel Thirion, Jean-Marc Daveau, Valentin Egloff, David Hély, Vincent Beroulle, Philippe Roche
2025	C	`conf`	Formal Analysis of Fault Propagation in Complex Digital Systems. MEMOCODE Damiano Zuccalà, Samuel Hon, Mohammad Reza Heidari Iman, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2024	J	`jnl`	Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach. J. Electron. Test. Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche
2024	—	`conf`	Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning. SBCCI Esther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche
2024	C	`conf`	Formal Fault Injection in Digital Blocks with Mined Assertions. MEMOCODE Damiano Zuccalà, Paul Breuil, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2024	B	`conf`	Formal Resilience Metric Characterization in Complex Digital Systems. ETS Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2023	—	`conf`	Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning. LATS Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche
2023	—	`conf`	Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2022	C	`conf`	Software Product Reliability Based on Basic Block Metrics Recomposition. IOLTS Tiziano Fiorucci, Giorgio Di Natale, Jean-Marc Daveau, Philippe Roche
2021	C	`conf`	Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems. IOLTS Tiziano Fiorucci, Jean-Marc Daveau, Giorgio Di Natale, Philippe Roche
2021	—	`conf`	FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. DFT Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain
2018	J	`jnl`	A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran
2017	—	`conf`	A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran
2016	—	`conf`	30% static power improvement on ARM Cortex ESSCIRC Fady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche
2015	—	`conf`	28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors. ESSCIRC Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche
2015	—	`conf`	8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. ISSCC Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2015	—	`conf`	Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test. IRPS Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid, Sylvain Clerc, Lirida A. B. Naviner, Philippe Roche
2015	—	`conf`	Partial triplication of a SPARC-V8 microprocessor using fault injection. LASCAS Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
2011	C	`conf`	An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. IOLTS Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
2010	J	`jnl`	Fast reliability analysis of combinatorial logic circuits using conditional probabilities. Microelectron. Reliab. Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
2010	—	`conf`	Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation. ICECS Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche
2010	—	`conf`	Verification of soft error detection mechanism through fault injection on hardware emulation platform. DSN Workshops Oscar Bailan, Umberto Rossi, Anne Wantens, Jean-Marc Daveau, Salvatore Nappi, Philippe Roche
2008	C	`conf`	Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS. IOLTS Philippe Roche, Mark Lysinger, Gilles Gasiot, Jean-Marc Daveau, Mehdi Zamanian, Pierre Dautriche
2004	B	`conf`	A retargetable register allocation framework for embedded processors. LCTES Jean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana
2002	Misc	`conf`	FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors. EMSOFT Valérie Bertin, Jean-Marc Daveau, Philippe Guillaume, Thierry Lepley, Denis Pilat, Claire Richard, Miguel Santana, Thomas Thery
2001	J	`jnl`	Automating the Design of SOCs Using Cores. IEEE Des. Test Comput. Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau
2000	J	`jnl`	Interlanguage Communication Synthesis for Heterogeneous Specifications. Des. Autom. Embed. Syst. Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya
1999	C	`conf`	Communication Interface Synthesis for Multilanguage Specifications. IEEE International Workshop on Rapid System Prototyping Fabiano Hessel, Philippe Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya
1998	J	`jnl`	Hardware/Software Co-Design Methodology for Design of Embedded Systems. Integr. Comput. Aided Eng. Mohamed Abid, Tarek Ben Ismail, Adel Changuel, Carlos A. Valderrama, Mohamed Romdhani, Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya
1998	—	`conf`	Hardware/software co-design of an ATM network interface card: a case study. CODES Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya
1997	J	`jnl`	Protocol selection and interface generation for HW-SW codesign. IEEE Trans. Very Large Scale Integr. Syst. Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya
1997	A	`conf`	Transformational partitioning for co-design of multiprocessor systems. ICCAD Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya
1996	J	`jnl`	A system-level communication synthesis approach for hardware/software systems. Microprocess. Microsystems Tarek Ben Ismail, Jean-Marc Daveau, Kevin O'Brien, Ahmed Amine Jerraya
1995	—	`conf`	Synthesis of system-level communication by an allocation-based approach. ISSS Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya