Jean-Luc Dekeyser

138 papers A* 1A 5B 4C 27Misc 3Journal 37Unranked 61

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	SCAC: Weakly-coupled execution model for massively parallel systems. Microprocess. Microsystems Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
2019	J	`jnl`	ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures. Int. J. Reconfigurable Comput. Karim M. A. Ali, Rabie Ben Atitallah, Abdessamad Ait El Cadi, Nizar Fakhfakh, Jean-Luc Dekeyser
2018	J	`jnl`	A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. J. Parallel Distributed Comput. Gilberto Ochoa-Ruiz, Pamela Wattebled, Maamar Touiza, Florent de Lamotte, El-Bay Bourennane, Samy Meftali, Jean-Luc Dekeyser, Jean-Philippe Diguet
2018	J	`jnl`	FPGA-Centric Design Process for Avionic Simulation and Test. IEEE Trans. Aerosp. Electron. Syst. Rabie Ben Atitallah, Venkatasubramanian Viswanathan, Nicolas Bélanger, Jean-Luc Dekeyser
2017	—	`conf`	Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation. ARC Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser
2016	—	`conf`	AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. MCSoC Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser
2016	C	`conf`	SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. PDP Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
2015	A	`conf`	A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications (Abstract Only). FPGA Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache
2015	Misc	`conf`	Adopting new learning strategies for computer architecture in higher education: case study: building the S3 microprocessor in 24 hours. WCAE Jean-Luc Dekeyser, A. Shadi Aljendi
2015	J	`jnl`	FPGA-based many-core System-on-Chip design. Microprocess. Microsystems Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
2015	Misc	`conf`	Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. FCCM Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser
2015	J	`jnl`	Towards an automation of the mutation analysis dedicated to model transformation. Softw. Test. Verification Reliab. Vincent Aranega, Jean-Marie Mottu, Anne Etien, Thomas Degueule, Benoit Baudry, Jean-Luc Dekeyser
2015	—	`conf`	Using hardware parallelism for reducing power consumption in video streaming applications. ReCoSoC Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser
2014	—	`conf`	A generic pixel distribution architecture for parallel video processing. ReConFig Karim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser
2014	J	`jnl`	Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design. Knowl. Eng. Rev. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
2014	—	`conf`	Communication-centric design for FMC based I/O system. ReCoSoC Mokhtar Bouain, Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser
2014	—	`conf`	Model-driven design flow for distributed control in reconfigurable FPGA systems. DASIP Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser
2014	A	`conf`	Redefining the role of FPGAs in the next generation avionic systems (abstract only). FPGA Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache
2013	J	`jnl`	A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. Integr. Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
2013	J	`jnl`	An MDE Approach for Automatic Code Generation from UML/MARTE to OpenCL. Comput. Sci. Eng. Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
2013	J	`jnl`	Decentralized control for dynamically reconfigurable FPGA systems. Microprocess. Microsystems Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
2013	C	`conf`	Master-Slave Control Structure for Massively Parallel System on Chip. DSD Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
2012	J	`jnl`	A fast MPSoC virtual prototyping for intensive signal processing applications. Microprocess. Microsystems Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser
2012	J	`jnl`	Abstract Clock-Based Design of a JPEG Encoder. IEEE Embed. Syst. Lett. Adolf Samir Abdallah, Abdoulaye Gamatié, Rabie Ben Atitallah, Jean-Luc Dekeyser
2012	—	`conf`	An efficient power estimation methodology for complex RISC processor-based platforms. ACM Great Lakes Symposium on VLSI Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar
2012	—	`conf`	Broadcast with mask on a massively parallel processing on a chip. HPCS Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
2012	—	`conf`	Distributed control for reconfigurable FPGA systems: A high-level design approach. ReCoSoC Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
2012	—	`conf`	Dynamic reconfiguration of modular I/O IP cores for avionic applications. ReConFig Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser
2012	C	`conf`	Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. RSP Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser
2012	J	`jnl`	Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. J. Syst. Archit. Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser
2012	—	`conf`	Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. ReConFig Gilberto Ochoa-Ruiz, Ouassila Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser
2012	—	`conf`	Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems. ReCoSoC Pamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser
2012	C	`conf`	Semi-distributed Control for FPGA-based Reconfigurable Systems. DSD Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
2012	J	`jnl`	System level modeling methodology of NoC design from UML-MARTE to VHDL. Des. Autom. Embed. Syst. Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
2011	J	`jnl`	A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. EURASIP J. Embed. Syst. Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai
2011	J	`jnl`	A Model-Driven Design Framework for Massively Parallel Embedded Systems. ACM Trans. Embed. Comput. Syst. Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Rabie Ben Atitallah, Anne Etien, Philippe Marquet, Jean-Luc Dekeyser
2011	J	`jnl`	A Modeling Approach based on UML/MARTE for GPU Architecture CoRR Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
2011	C	`conf`	A model-driven based framework for rapid parallel SoC FPGA prototyping. International Symposium on Rapid System Prototyping Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser
2011	J	`jnl`	A multi-level design methodology of multistage interconnection network for MPSOCs. Int. J. Comput. Appl. Technol. Yassine Aydi, Mouna Baklouti, Mohamed Abid, Jean-Luc Dekeyser
2011	—	`conf`	A prototyping environment for high performance reconfigurable computing. ReCoSoC George Afonso, Rabie Ben Atitallah, Alexander Loyer, Jean-Luc Dekeyser, Nicolas Bélanger, Martial Rubio
2011	—	`conf`	A system level power consumption estimation for MPSoC. SoC Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser
2011	J	`jnl`	Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines CoRR Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser, Yvonnick Le Menach
2011	—	`conf`	Fast and accurate hybrid power estimation methodology for embedded systems. DASIP Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser
2011	—	`conf`	FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. DASIP Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser
2011	—	`conf`	High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. DASIP Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser
2011	C	`conf`	Hybrid system level power consumption estimation for FPGA-based MPSoC. ICCD Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Smaïl Niar, Eric Senn, Jean-Luc Dekeyser
2011	J	`jnl`	Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture. Tech. Sci. Informatiques Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
2011	J	`jnl`	Programming Massively Parallel Architectures using MARTE: a Case Study CoRR Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Jean-Luc Dekeyser
2011	—	`conf`	Toward generic and adaptive avionic test systems. AHS George Afonso, Rabie Ben Atitallah, Nicolas Bélanger, Martial Rubio, Stephan Stilkerich, Jean-Luc Dekeyser
2011	J	`jnl`	Using an Alternative Trace for QVT. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. Vincent Aranega, Anne Etien, Jean-Luc Dekeyser
2010	—	`conf`	A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. ISSPIT Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki
2010	—	`conf`	Correct and energy-efficient design of SoCs: The H.264 encoder case study. SoC Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
2010	—	`conf`	Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. DASIP Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
2010	B	`conf`	IP Based Configurable SIMD Massively Parallel SoC. FPL Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
2010	C	`conf`	Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
2010	J	`jnl`	Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines CoRR Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'h, Yvonnick Le Menach, Jean-Luc Dekeyser
2010	—	`conf`	Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. ARC Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
2010	J	`jnl`	Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. J. Syst. Archit. Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid
2010	J	`jnl`	Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. Int. J. Embed. Syst. Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser
2010	—	`conf`	Traceability for Mutation Analysis in Model Transformation. MoDELS (Workshops) Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
2009	C	`conf`	A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. DSD Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid
2009	—	`conf`	A multi level functional verification of multistage interconnection network for MPSOC. ICECS Yassine Aydi, Ramzi Tligue, Maissa Elleuch, Mohamed Abid, Jean-Luc Dekeyser
2009	J	`jnl`	High level modeling of Dynamic Reconfigurable FPGAs. Int. J. Reconfigurable Comput. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
2009	C	`conf`	Model-Driven Design of Embedded Multimedia Applications on SoCs. DSD Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
2009	J	`jnl`	Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Comput. Pract. Exp. Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
2009	C	`conf`	Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. AICCSA Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
2009	—	`conf`	Traceability Mechanism for Error Localization in Model Transformation. ICSOFT (1) Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
2009	—	`conf`	Using Trace to Situate Errors in Model Transformations. ICSOFT (Selected Papers) Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser
2008	C	`conf`	A Graphical Framework for High Performance Computing Using An MDE Approach. PDP Julien Taillard, Frédéric Guyomarc'h, Jean-Luc Dekeyser
2008	—	`conf`	An MPSoC architecture for the Multiple Target Tracking application in driver assistant system. ASAP Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser
2008	—	`conf`	MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. ESTIMedia Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser
2008	C	`conf`	MARTE-based Design of a Multimedia Application and Formal Analysis. FDL Adolf Samir Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser
2008	C	`conf`	Modeling and Formal Validation of High-Performance Embedded Systems. ISPDC Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
2008	J	`jnl`	Safe design of high-performance embedded systems in an MDE framework. Innov. Syst. Softw. Eng. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
2008	J	`jnl`	Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP J. Embed. Syst. Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser
2008	—	`conf`	Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. DIPES Sebastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser
2008	—	`conf`	Using an MDE Approach for Modeling of Interconnection Networks. ISPAN Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser
2007	B	`conf`	A Design Flow to Map Parallel Applications onto FPGAs. FPL Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
2007	B	`conf`	An MPSoC Performance Estimation Framework Using Transaction Level Modeling. RTCSA Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
2007	—	`conf`	An Open Framework for Detailed Hardware Modeling. SIES Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser
2007	C	`conf`	MARTE: UML-based Hardware Design from Modelling to Simulation. FDL Safouan Taha, Ansgar Radermacher, Sébastien Gérard, Jean-Luc Dekeyser
2007	—	`conf`	Massively parallel processing on a chip. Conf. Computing Frontiers Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
2007	—	`conf`	Model Transformations for the Compilation of Multi-processor Systems-on-Chip. GTTSE Éric Piel, Philippe Marquet, Jean-Luc Dekeyser
2007	C	`conf`	Model Transformations from a Data Parallel Formalism towards Synchronous Languages. FDL Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser
2007	—	`conf`	Multilevel MPSOC simulation using an MDE approach. SoCC Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser
2007	—	`conf`	Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
2006	J	`jnl`	A universal performance factor for multi-criteria evaluation of multistage interconnection networks. Future Gener. Comput. Syst. Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson
2006	—	`conf`	Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser
2006	C	`conf`	FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. DSD Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
2006	—	`conf`	Multilevel MPSoC Performance Evaluation Using MDE Approach. SoC Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
2006	A	`conf`	Real-time systems for multiprocessor architectures. IPDPS Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
2006	—	`conf`	Safe Design Methodology for an Intelligent Cruise Control System with GPS. VTC Fall Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser
2006	C	`conf`	UML2 Profile for Modeling Controlled Data Parallel Applications. FDL Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser, Pierre Boulet
2005	Misc	`conf`	Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. PPAM Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
2005	C	`conf`	Embed Scripting inside SystemC. FDL J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser
2005	—	`conf`	Mode-Automata Based Methodology for Scade. HSCC Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet
2005	—	`conf`	Model Driven Engineering for Regular MPSoC Co-design. ReCoSoC Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena
2005	—	`conf`	Scalable Multistage Network for Multiprocessor System-on-Chip Design. ISPAN Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson
2005	A	`conf`	Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. MoDELS Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet
2005	C	`conf`	Traceability and Interoperability in Models Transformations. FDL Lossan Bonde, Pierre Boulet, Jean-Luc Dekeyser
2004	—	`conf`	An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. IWSOC Samy Meftali, Jean-Luc Dekeyser
2004	C	`conf`	An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). FDL E. Turbatu, Samy Meftali, Smaïl Niar, Jean-Luc Dekeyser
2004	C	`conf`	MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. FDL M. Samyn, Samy Meftali, Jean-Luc Dekeyser
2004	C	`conf`	Metamodels and MDA Transformations for Embedded Systems. FDL Lossan Bonde, Cédric Dumoulin, Jean-Luc Dekeyser
2004	C	`conf`	Regular Hardware Architecture Modeling with UML2. FDL Arnaud Cuccuru, Pierre Boulet, Jean-Luc Dekeyser
2004	—	`conf`	SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. Virtual Enterprises and Collaborative Networks Samy Meftali, Jean-Luc Dekeyser
2004	C	`conf`	The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks. PDP Ahmad Chadi Aljundi, Jean-Luc Dekeyser
2004	—	`conf`	UML2 as an ADL Hierarchichal Hardware Modeling. IFIP-WADL Arnaud Cuccuru, Philippe Marquet, Jean-Luc Dekeyser
2003	A	`conf`	A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks. IPDPS Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar Kechadi, Isaac D. Scherson
2003	—	`conf`	An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks. PDCS Ahmad Chadi Aljundi, Jean-Luc Dekeyser, Isaac D. Scherson
2003	—	`conf`	Distributed Process Networks - Using Half FIFO Queues in CORBA. PARCO Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser, T. Theeuwen
2003	C	`conf`	Interoperability between Design and Simulation Tools using Model Transformation Techniques. FDL Cédric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, S. Pulon, G. Cristau
2003	C	`conf`	MDA for SoC Design, Intensive Signal Processing Experiment. FDL Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet
2002	—	`conf`	GASPARD - A Visual Parallel Programming Environment. PARELEC Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet
2002	J	`jnl`	Towards Distributed Process Networks with CORBA. Parallel Distributed Comput. Pract. Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser
2001	B	`conf`	Compilation Principle of a Specification Language Dedicated to Signal Processing. PaCT Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser
2001	C	`conf`	Visual Data-Parallel Programming for Signal Processing Applications. PDP Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure
2000	—	`conf`	High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns. VECPAR Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, Stéphane Clénet
2000	—	`conf`	Parallelization of a 3D Magnetostatic Code Using High Performance Fortran. PARELEC Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, Georges Marques
1998	—	`conf`	DPFS: A Data-Parallel File System Environment. HPCN Europe Dominique Sueur, Jean-Luc Dekeyser, Philippe Marquet
1998	J	`jnl`	Data-Parallel Load Balancing Strategies. Parallel Comput. Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
1998	—	`conf`	Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures. HPCN Europe Fabien Banse, Jean-Luc Dekeyser, Renaud Fauquembergue, François Dessenne
1997	J	`jnl`	Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems. Parallel Comput. M. Tahar Kechadi, Jean-Luc Dekeyser
1997	—	`conf`	Data Parallel File System. PP Jean-Luc Dekeyser, Dominique Sueur
1997	J	`jnl`	Hpf-Builder: a Visual Environment To Transform Fortran 90 Codes To Hpf. Int. J. High Perform. Comput. Appl. Jean-Luc Dekeyser, Christian Lefebvre
1997	—	`conf`	Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder. PP Jean-Luc Dekeyser, Christian Lefebvre
1996	—	`conf`	Dynamic Redistribution on Heterogeneous Parallel Computers. Euro-Par, Vol. I Dominique Sueur, Jean-Luc Dekeyser
1996	—	`conf`	Irregular Data-Parallel Objects in C++. VECPAR Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire, Philippe Marquet
1996	—	`conf`	Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder. ICIP (2) David Galinec, Jean-Luc Dekeyser, Philippe Marquet
1996	—	`conf`	Supporting Irregular and Dynamic Computations in Data Parallel Languages. The Data Parallel Programming Model Jean-Luc Dekeyser, Philippe Marquet
1995	—	`conf`	Analysis of Synchronous Dynamic Load Balancing Algorithms. PARCO Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
1994	—	`conf`	A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. HPCN Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
1994	J	`jnl`	A Geometrical Data-Parallel Language. ACM SIGPLAN Notices Jean-Luc Dekeyser, Dominique Lazure, Philippe Marquet
1994	—	`conf`	Dynamic Load Balancing on SIMD Data-Parallel Computers. EUROSIM Cyril Fonlupt, Jean-Luc Dekeyser, Philippe Marquet
1993	—	`conf`	HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. HCI (2) Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet
1992	A*	`conf`	Performance improvement for vector pipeline multiprocessor systems using a disordered execution model. ISCA M. Tahar Kechadi, Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux
1990	J	`jnl`	EVA: an explicit vector language. ACM SIGPLAN Notices Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux
1990	J	`jnl`	Vector addressing processor for direct and indirect accesses. Microprocessing and Microprogramming Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux