Jean-Luc Béchennec

60 papers A* 1A 3B 1C 10Misc 5Journal 17Unranked 23
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Study in Specification and Hardware Runtime Verification of Critical Embedded Software.
IEEE Trans. Dependable Secur. Comput.
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2025 C conf
Circadia: Checkpointing for Intermittent Computing in AI Driven Applications.
DSD
Matthieu Rodet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2025 J jnl
Model-Checking of Concurrent Real-Time Software Using High-Level Colored Time Petri Nets with Stopwatches.
Cybern. Syst.
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
2025 Misc conf
Verifying Timed Properties of Programs in IoT nodes using Parametric Time Petri Nets.
SAC
Étienne André, Jean-Luc Béchennec, Sudipta Chattopadhyay, Sébastien Faucou, Didier Lime, Dylan Marinho, Olivier H. Roux, Jun Sun
2024 B conf
EarlyBird: Energy belongs to those who wake up early.
RTCSA
Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2024 A conf
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems.
CGO
Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2023 J jnl
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems.
Discret. Event Dyn. Syst.
Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux
2023 J jnl
Formal verification process of the compliance of a multicore AUTOSAR OS.
Softw. Qual. J.
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
2023 A conf
Securing a RISC-V architecture: A dynamic approach.
DATE
Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon
2022 C conf
Formal Verification of the Inter-core Synchronization of a Multi-core RTOS Kernel.
ICFEM
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
2022 C conf
High-level Colored Time Petri Nets for true concurrency modeling in real-time software.
CoDIT
Imane Haur, Jean-Luc Béchennec, Olivier H. Roux
2021 — conf
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds.
Audio Mostly Conference
Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange
2021 Misc conf
Formal schedulability analysis based on multi-core RTOS model.
RTNS
Imane Haur, Jean-Luc Béchennec, Olivier Henri Roux
2021 J jnl
Logical time control of concurrent DES.
Discret. Event Dyn. Syst.
Jean-Luc Béchennec, Didier Lime, Olivier H. Roux
2020 Misc conf
Requirement specification and model-checking of a real-time scheduler implementation.
RTNS
Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche
2019 — conf
Control of DES with Urgency, Avoidability and Ineluctability.
ACSD
Jean-Luc Béchennec, Didier Lime, Olivier H. Roux
2018 Misc conf
Formal approach for a verified implementation of Global EDF in Trampoline.
RTNS
Khaoula Boukir, Jean-Luc Béchennec, Anne-Marie Déplanche
2018 C conf
Formal model-based conformance verification of an OSEK/VDX compliant RTOS.
CoDIT
Jean-Luc Béchennec, Olivier Henry Roux, Tigori Kabland Toussaint Gautier
2018 — conf
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems.
AHS
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday
2018 Misc conf
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection.
EDCC
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2018 J jnl
Testing Real-Time Systems With Runtime Enforcement.
IEEE Des. Test
Jean-Luc Béchennec, Sébastien Faucou, Olivier H. Roux, Matthias Brun, Louis-Marie Givel
2017 J jnl
Formal Model-Based Synthesis of Application-Specific Static RTOS.
ACM Trans. Embed. Comput. Syst.
Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Sébastien Faucou, Olivier Henry Roux
2017 C conf
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction.
VECoS
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
2016 — conf
BEST: a Binary Executable Slicing Tool.
WCET
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
2016 — conf
Hardware runtime verification of embedded software in SoPC.
SIES
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2016 — conf
Testing real-time embedded software using runtime enforcement.
SIES
Louis-Marie Givel, Jean-Luc Béchennec, Matthias Brun, Sébastien Faucou, Olivier H. Roux
2015 — conf
Formal Synthesis of Optimal RTOS.
HPCC/CSS/ICESS
Tigori Kabland Toussaint Gautier, Jean-Luc Béchennec, Olivier Henry Roux
2015 J jnl
STM-HRT: A Robust and Wait-Free STM for Hard Real-Time Multicore Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Sylvain Cotard, Audrey Queudet, Jean-Luc Béchennec, Sébastien Faucou, Yvon Trinquet
2014 — conf
Improving processor hardware compiled cycle accurate simulation using program abstraction.
SimuTools
Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet
2014 C conf
Reactive embedded device driver synthesis using logical timed models.
SIMULTECH
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux
2013 C conf
Device driver synthesis for embedded systems.
ETFA
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux
2013 — conf
Timing Analysis of Binary Programs with UPPAAL.
ACSD
Franck Cassez, Jean-Luc Béchennec
2012 — conf
A Data Flow Monitoring Service Based on Runtime Verification for AUTOSAR.
HPCC-ICESS
Sylvain Cotard, Sébastien Faucou, Jean-Luc Béchennec, Audrey Queudet, Yvon Trinquet
2012 J jnl
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation.
J. Syst. Archit.
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet
2011 J jnl
An Architecture Description Language for Embedded Hardware Platforms.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol.
Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem
2011 J jnl
Computation of WCET using Program Slicing and Real-Time Model-Checking
CoRR
Jean-Luc Béchennec, Franck Cassez
2011 — conf
Extending Harmless architecture description language for embedded real-time systems validation.
SIES
Jean-Luc Béchennec, Mikaël Briday, Valere Alibert
2010 — conf
ViPER: a lightweight approach to the simulation of distributed and embedded software.
SimuTools
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif
2009 — conf
Instruction set simulator generation using HARMLESS, a new hardware architecture description language.
SimuTools
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
2008 — conf
Simulator generation using an automaton based pipeline model for timing analysis.
IMCSIT
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
2006 C conf
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification.
ETFA
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet
2002 J jnl
Increasing hardware data prefetching performance using the second-level cache.
J. Syst. Archit.
Nathalie Drach, Jean-Luc Béchennec, Olivier Temam
2000 A* conf
The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches.
HPCA
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
1999 — conf
A Parallel Algorithm for 3D Geometry Transformations in OpenGL.
Euro-Par
Julien Sébot, Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
1999 — conf
PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation.
Euro-Par
Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec
1999 — conf
Two Schemes to Improve the Performance of a
Euro-Par
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
1998 — conf
ASF: a teaching and rsearch object-oriented simulation tool for computer architecture design and performance evaluation.
WCAE@ISCA
Jean-Luc Béchennec
1998 A conf
Evaluation of High Performance Multicache Parallel Texture Mapping.
International Conference on Supercomputing
Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
1997 — conf
Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces.
EUROMICRO
A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble
1993 J jnl
A Communication Architecture for a Massively Parallel Message-Passing Multicomputer.
J. Parallel Distributed Comput.
Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet
1993 — conf
A Parralel Architecture Based on Compiled Communication Schemes.
PARCO
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
1993 — conf
Balanced Distributed Memory Parallel Computers.
ICPP (1)
Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
1993 J jnl
Hardware features of the static communication network of a parallel architecture.
Microprocess. Microprogramming
Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
1993 C conf
Static computation of standard linear algebra subroutines for PTAH.
PDP
E. Daugeras, Jean-Luc Béchennec, Franck Cappello
1992 J jnl
Design of the processing node of the PTAH 64 parallel computer.
Microprocess. Microprogramming
Franck Cappello, Jean-Luc Béchennec, J.-L. Glavitto
1992 — conf
PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing.
PARLE
Franck Cappello, Jean-Luc Béchennec, Jean-Louis Giavitto
1991 J jnl
3D hardware packages for parallel architectures.
Microprocessing and Microprogramming
Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble
1990 J jnl
A risc central processing unit for a massivelly parallel architecture.
Microprocessing and Microprogramming
Franck Cappello, Jean-Luc Béchennec, Daniel Etiemble
1988 C conf
A highly parallel processor with an instruction set including relational algebra.
ICCD
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec
1987 — conf
The Database Processor 'RAPID'.
IWDM
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé