Jean-Luc Beuchat

53 papers A 3B 4C 4Misc 1Journal 33Unranked 8
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Digital Identity in the Hands of Swiss Citizens.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Valon Rexhepi
2017 J jnl
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl.
J. Parallel Distributed Comput.
Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki
2016 J jnl
Guest Editorial: Introduction to the Special Section on Emerging Security Trends for Biomedical Computations, Devices, and Infrastructures.
IEEE ACM Trans. Comput. Biol. Bioinform.
Mehran Mozaffari Kermani, Reza Azarderakhsh, Kui Ren, Jean-Luc Beuchat
2014 J jnl
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki
2013 J jnl
Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA.
IACR Cryptol. ePrint Arch.
Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki
2012 J jnl
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl.
IACR Cryptol. ePrint Arch.
Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki
2012 — conf
Compact Implementation of Threefish and Skein on FPGA.
NTMS
Nuray At, Jean-Luc Beuchat, Ismail San
2012 J jnl
Compact Implementation of Threefish and Skein on FPGA.
IACR Cryptol. ePrint Arch.
Nuray At, Jean-Luc Beuchat, Ismail San
2012 B conf
Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves.
CT-RSA
Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals
2011 J jnl
A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
2011 J jnl
A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO.
J. Cryptogr. Eng.
Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
2011 J jnl
Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves.
IEEE Trans. Computers
Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez
2010 J jnl
A Compact FPGA Implementation of the SHA-3 Candidate ECHO.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
2010 J jnl
Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
2010 — conf
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA.
FPT
Jean-Luc Beuchat, Eiji Okamoto, Teppei Yamazaki
2010 J jnl
FPGA and ASIC implementations of the eta
Comput. Electr. Eng.
Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto
2010 C conf
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves.
Pairing
Jean-Luc Beuchat, Jorge Enrique González-Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, Tadanori Teruya
2010 J jnl
High-Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Jorge Enrique González-Díaz, Shigeo Mitsunari, Eiji Okamoto, Francisco Rodríguez-Henríquez, Tadanori Teruya
2010 J jnl
Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves.
IACR Cryptol. ePrint Arch.
Diego F. Aranha, Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals
2009 J jnl
Fast Architectures for the eta
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez
2009 A conf
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.
CHES
Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez
2009 J jnl
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez
2009 B conf
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves.
CANS
Jean-Luc Beuchat, Emmanuel López-Trejo, Luis Martínez-Ramos, Shigeo Mitsunari, Francisco Rodríguez-Henríquez
2009 J jnl
Multi-core Implementation of the Tate Pairing over Supersingular Elliptic Curves.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Emmanuel López-Trejo, Luis Martínez-Ramos, Shigeo Mitsunari, Francisco Rodríguez-Henríquez
2008 J jnl
A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez
2008 C conf
A Comparison between Hardware Accelerators for the Modified Tate Pairing over F
Pairing
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Francisco Rodríguez-Henríquez
2008 J jnl
A Pipelined Karatsuba-Ofman Multiplier over GF(3
IACR Cryptol. ePrint Arch.
Nidia Cortez-Duarte, Francisco Rodríguez-Henríquez, Jean-Luc Beuchat, Eiji Okamoto
2008 J jnl
Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three.
IEEE Trans. Computers
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi
2008 J jnl
Automatic Generation of Modular Multipliers for FPGA Applications.
IEEE Trans. Computers
Jean-Luc Beuchat, Jean-Michel Muller
2008 J jnl
FPGA and ASIC Implementations of the eta
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto
2007 C conf
A Coprocessor for the Final Exponentiation of the
WAIFI
Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
2007 J jnl
A Coprocessor for the Final Exponentiation of the eta
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
2007 J jnl
A Refined Algorithm for the eta
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
2007 J jnl
Algorithms and Arithmetic Operators for Computing the eta
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi
2007 C conf
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation.
IEEE Symposium on Computer Arithmetic
Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
2007 A conf
Arithmetic Operators for Pairing-Based Cryptography.
CHES
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
2007 J jnl
Arithmetic Operators for Pairing-Based Cryptography.
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
2007 J jnl
Further Comments on "Residue-to-Binary Converters Based on New Chinese Remainder Theorems"
CoRR
Jean-Luc Beuchat
2007 — conf
Multiplication over F
ARC
Jean-Luc Beuchat, Takanori Miyoshi, Yoshihito Oyama, Eiji Okamoto
2006 J jnl
An Algorithm for the η
IACR Cryptol. ePrint Arch.
Jean-Luc Beuchat, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto
2005 — conf
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.
ASAP
Jean-Luc Beuchat, Jean-Michel Muller
2004 J jnl
Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA.
Tech. Sci. Informatiques
Jean-Luc Beuchat, Arnaud Tisserand
2003 B conf
FPGA Implementations of the RC6 Block Cipher.
FPL
Jean-Luc Beuchat
2003 — conf
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.
ASAP
Jean-Luc Beuchat
2003 A conf
Some Modular Adders and Multipliers for Field Programmable Gate Arrays.
IPDPS
Jean-Luc Beuchat
2002 J jnl
Approches matérielles et logicielles de l'algorithme de chiffrement IDEA.
Tech. Sci. Informatiques
Jean-Luc Beuchat, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Christof Teuscher, Francisco J. Gómez, Eduardo Sanchez
2002 B conf
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.
FPL
Jean-Luc Beuchat, Arnaud Tisserand
2000 J jnl
Von Neumann's 29-state cellular automaton: a hardware implementation.
IEEE Trans. Educ.
Jean-Luc Beuchat, Jacques-Olivier Haenni
1999 — conf
An On-Line Arithmetic-Based Reconfigurable Neuroprocessor.
IPPS/SPDP Workshops
Jean-Luc Beuchat, Eduardo Sanchez
1999 J jnl
Static and Dynamic Configurable Systems.
IEEE Trans. Computers
Eduardo Sanchez, Moshe Sipper, Jacques-Olivier Haenni, Jean-Luc Beuchat, André Stauffer, Andrés Pérez-Uribe
1999 — conf
Using On-Line Arithmetic and Reconfiguration for Neuroprocessor Implementations.
IWANN (2)
Jean-Luc Beuchat, Eduardo Sanchez
1998 — conf
Hardware Reconfigurable Neural Networks.
IPPS/SPDP Workshops
Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez
1998 Misc conf
RENCO: A Reconfigurable Network Computer.
FCCM
Jacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez