Jean-Didier Legat

98 papers A* 1A 11B 7C 11Misc 4Journal 29Unranked 35

Year	Rank	Type	Title / Venue / Authors
2020	C	`conf`	A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. ISCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2020	J	`jnl`	A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas. CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2019	J	`jnl`	A 0.086-mm IEEE Trans. Biomed. Circuits Syst. Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol
2019	C	`conf`	A 65-nm 738k-Synapse/mm ISCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2019	J	`jnl`	MorphIC: A 65-nm 738k-Synapse/mm CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2019	J	`jnl`	MorphIC: A 65-nm 738k-Synapse/mm IEEE Trans. Biomed. Circuits Syst. Charlotte Frenkel, Jean-Didier Legat, David Bol
2018	J	`jnl`	A 0.086-mm CoRR Charlotte Frenkel, Jean-Didier Legat, David Bol
2017	—	`conf`	A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors. BioCAS Charlotte Frenkel, Jean-Didier Legat, David Bol
2017	C	`conf`	A fully-synthesized 20-gate digital spike-based synapse with embedded online learning. ISCAS Charlotte Frenkel, Giacomo Indiveri, Jean-Didier Legat, David Bol
2016	C	`conf`	Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. VLSI-SoC Charlotte Frenkel, Jean-Didier Legat, David Bol
2016	J	`jnl`	Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
2015	—	`conf`	A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. ReCoSoC Charlotte Frenkel, Jean-Didier Legat, David Bol
2014	J	`jnl`	A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
2014	C	`conf`	Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes. ISCAS François Botman, Julien De Vos, Sebastien Bernard, François Stas, Jean-Didier Legat, David Bol
2014	J	`jnl`	Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. François Botman, David Bol, Jean-Didier Legat, Kaushik Roy
2014	—	`conf`	Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
2013	—	`conf`	An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
2013	J	`jnl`	SleepWalker: A 25-MHz 0.4-V Sub-mm IEEE J. Solid State Circuits David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
2012	—	`conf`	A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. ISSCC David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat
2012	J	`jnl`	A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks. ACM Trans. Reconfigurable Technol. Syst. Angelo Kuti Lusala, Jean-Didier Legat
2012	—	`conf`	A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications. NEWCAS Angelo Kuti Lusala, Jean-Didier Legat
2012	J	`jnl`	Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks. Int. J. Reconfigurable Comput. Angelo Kuti Lusala, Jean-Didier Legat
2012	—	`conf`	MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs. ReCoSoC Renaud Van Langendonck, Angelo Kuti Lusala, Jean-Didier Legat
2011	—	`conf`	A SDM-TDM based circuit-switched router for on-chip networks. ReCoSoC Angelo Kuti Lusala, Jean-Didier Legat
2011	—	`conf`	A new mechanism to reduce congestion on TDM networks-on-chips. ReCoSoC Daniel Vergeylen, Angelo Kuti Lusala, Jean-Didier Legat
2011	C	`conf`	Combining sdm-based circuit switching with packet switching in a NoC for real-time applications. ISCAS Angelo Kuti Lusala, Jean-Didier Legat
2011	J	`jnl`	Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. J. Cryptogr. Eng. Cédric Hocquet, Dina Kamel, Francesco Regazzoni, Jean-Didier Legat, Denis Flandre, David Bol, François-Xavier Standaert
2010	—	`conf`	A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks. ReConFig Angelo Kuti Lusala, Jean-Didier Legat
2010	—	`conf`	A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms. DASIP Bertrand Rousseau, Philippe Manet, Igor Loiselle, Jean-Didier Legat, Hans Vandierendonck
2010	C	`conf`	Combining circuit and packet switching with bus architecture in a NoC for real-time applications. ISCAS Angelo Kuti Lusala, Jean-Didier Legat
2010	J	`jnl`	Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels. ACM Trans. Design Autom. Electr. Syst. David Bol, Denis Flandre, Jean-Didier Legat
2010	C	`conf`	Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. ISCAS David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat
2010	—	`conf`	The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic. ESSCIRC David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat
2010	J	`jnl`	ULPFA: A New Efficient Design of a Power-Aware Full Adder. IEEE Trans. Circuits Syst. I Regul. Pap. Ilham Hassoune, Denis Flandre, Ian O'Connor, Jean-Didier Legat
2009	B	`conf`	Flexible embedded system for sensor integration and custom data processing in an automotive application. IWCMC Lotfi Guedria, Damien Hubaux, Mathieu Ocaña, Jean-Didier Legat
2009	J	`jnl`	Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Trans. Very Large Scale Integr. Syst. David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2009	A	`conf`	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ISLPED David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat
2009	A	`conf`	Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. ISLPED David Bol, Denis Flandre, Jean-Didier Legat
2008	J	`jnl`	An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications. EURASIP J. Embed. Syst. Philippe Manet, Daniel Maufroid, Leonardo Tosi, Grégory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier, Bertrand Rousseau, Paul Gelineau
2008	C	`conf`	Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ICCD David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2008	—	`conf`	Impact of Technology Scaling on Digital Subthreshold Circuits. ISVLSI David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2007	—	`conf`	Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices. ICECS David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2007	—	`conf`	By-passing the out-of-order execution pipeline to increase energy-efficiency. Conf. Computing Frontiers Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat
2007	J	`jnl`	Dynamic differential self-timed logic families for robust and low-power security ICs. Integr. Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat
2007	J	`jnl`	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder. J. Multiple Valued Log. Soft Comput. David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat
2007	A	`conf`	Enabling certification for dynamic partial reconfiguration using a minimal flow. DATE Bertrand Rousseau, Philippe Manet, D. Galerin, D. Merkenbreack, Jean-Didier Legat, F. Dedeken, Yves Gabriel
2007	A	`conf`	Interactive presentation: RECOPS: reconfiguring programmable devices for military hardware electronics. DATE Philippe Manet, Daniel Maufroid, Leonardo Tosi, Marco Di Ciano, Olivier Mulertt, Yves Gabriel, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba
2007	B	`conf`	NoC Implementation in FPGA Using Torus Topology. FPL Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat
2006	J	`jnl`	A Flexible Hardware JPEG 2000 Decoder for Digital Cinema. IEEE Trans. Circuits Syst. Video Technol. Antonin Descampe, François-Olivier Devaux, Gaël Rouvroy, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq
2006	A	`conf`	Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. DATE Hans Vandierendonck, Philippe Manet, Jean-Didier Legat
2006	J	`jnl`	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. J. Low Power Electron. Philippe Manet, Renaud Ambroise, David Bol, Marc Baltus, Jean-Didier Legat
2006	—	`conf`	Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards. ASAP Guerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat
2006	J	`jnl`	Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks. Microelectron. J. Ilham Hassoune, François Macé, Denis Flandre, Jean-Didier Legat
2006	—	`conf`	Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo
2005	—	`conf`	A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. PATMOS François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2005	—	`conf`	Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. PATMOS Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat
2005	—	`conf`	Practical Evaluation of a Radial Soft Hash Algorithm. ITCC (2) François-Xavier Standaert, Frédéric Lefèbvre, Gaël Rouvroy, Benoît Macq, Jean-Jacques Quisquater, Jean-Didier Legat
2004	—	`conf`	An efficient FPGA implementation of a flexible JPEG2000 decoder for Digital Cinema. EUSIPCO Antonin Descampe, François-Olivier Devaux, Gaël Rouvroy, Benoît Macq, Jean-Didier Legat
2004	—	`conf`	Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. ITCC (2) Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2004	—	`conf`	Hardware implementation of a fingerprinting algorithm suited for digital cinema. EUSIPCO Gaël Rouvroy, Frédéric Lefèbvre, François-Xavier Standaert, Benoît Macq, Jean-Jacques Quisquater, Jean-Didier Legat
2004	A*	`conf`	ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware. FSE François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2004	—	`conf`	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. PATMOS Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre
2004	—	`conf`	Reconfigurable hardware solutions for the digital rights management of digital cinema. Digital Rights Management Workshop Gaël Rouvroy, François-Xavier Standaert, Frédéric Lefèbvre, Jean-Jacques Quisquater, Benoît Macq, Jean-Didier Legat
2003	A	`conf`	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. FPGA François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2003	J	`jnl`	A survey on industrial vision systems, applications, tools. Image Vis. Comput. Elias N. Malamas, Euripides G. M. Petrakis, Michalis E. Zervakis, Laurent Petit, Jean-Didier Legat
2003	J	`jnl`	Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000. IEEE Trans. Circuits Syst. Video Technol. Grégory Dillen, Benoît Georis, Olivier Cantineau, Jean-Didier Legat
2003	B	`conf`	Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. FPL Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2003	A	`conf`	Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. FPGA Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2003	A	`conf`	Efficient FPGA Implementation of Block Cipher MISTY1. IPDPS Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2003	A	`conf`	Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. CHES François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2003	J	`jnl`	Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. IEEE Trans. Computers Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
2002	B	`conf`	A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. FPL Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat
2002	A	`conf`	A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results. CHES François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
2002	B	`conf`	An FPGA Implementation of the Linear Cryptanalysis. FPL François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
2002	—	`conf`	RASH: RAdon soft hash algorithm. EUSIPCO Frédéric Lefèbvre, Benoît Macq, Jean-Didier Legat
2001	A	`conf`	Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. IPDPS Jean-Pierre David, Tony Postiau, Paul Fisette, Jean-Didier Legat
2000	J	`jnl`	A dedicated DSP architecture for discrete wavelet transform. Integr. Comput. Aided Eng. Pierre Desneux, Jean-Didier Legat
1999	—	`conf`	A Graph-Oriented Task Manager for Small Multiprocessor Systems. Euro-Par Xavier Verians, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq
1999	—	`conf`	A New Parallelism Management Scheme for Multiprocessor Systems. ACPC Xavier Verians, Jean-Didier Legat, Jean-Jacques Quisquater, Benoît Macq
1999	—	`conf`	Architecture of security management unit for safe hosting of multiple agents. Security and Watermarking of Multimedia Contents Tanguy Gilmont, Jean-Didier Legat, Jean-Jacques Quisquater
1999	—	`conf`	Enhancing Security in the Memory Management Unit. EUROMICRO Tanguy Gilmont, Jean-Didier Legat, Jean-Jacques Quisquater
1999	—	`conf`	Fine grain parallelization of multibody system equations of motion. PARCO Tony Postiau, Paul Fisette, Jean-Didier Legat
1998	C	`conf`	A Data-Flow Oriented Co-Design for Reconfigurable Systems. International Workshop on Rapid System Prototyping Jean-Pierre David, Jean-Didier Legat
1998	J	`jnl`	Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit. J. VLSI Signal Process. Olivier Cantineau, Laurent Petit, Jean-Didier Legat
1998	—	`conf`	Efficient Parallelisation of an MPEG-2 Codec on a TMS320C80 Video Processor. ICIP (3) Olivier Cantineau, Jean-Didier Legat
1998	J	`jnl`	Image compression by self-organized Kohonen map. IEEE Trans. Neural Networks C. Amerijckx, Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1998	J	`jnl`	Selective prediction error transmission using motion information. Signal Process. Image Commun. Emmanuel Hanssens, Bertrand Chupeau, Jean-Didier Legat, Benoît Macq
1996	—	`conf`	Resolution reduction by growth of zones for visual prosthesis. ICIP (1) Tanguy Gilmont, Xavier Verians, Jean-Didier Legat, Claude Veraart
1995	Misc	`conf`	A Practical View of Suboptimal Bayesian Classification with Radial Gaussian Kernels. IWANN Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1995	Misc	`conf`	A VLSI System for Neural Bayesian and LVQ Classification. IWANN Philippe Thissen, Michel Verleysen, Jean-Didier Legat, Jordi Madrenas, Jordi Domínguez
1995	—	`conf`	A statistical neural network for high-dimensional vector classification. ICNN Michel Verleysen, Jean-Luc Voz, Philippe Thissen, Jean-Didier Legat
1995	Misc	`conf`	An Associative Processor Dedicated to Classification by Neural Methods. IWANN Philippe Thissen, Michel Verleysen, Jean-Didier Legat
1995	B	`conf`	Suboptimal Bayesian classification by vector quantization with small clusters. ESANN Jean-Luc Voz, Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993	J	`jnl`	Analog implementation of a Kohonen map with on-chip learning. IEEE Trans. Neural Networks Damien Macq, Michel Verleysen, Paul G. A. Jespers, Jean-Didier Legat
1993	Misc	`conf`	Linear Vector Classification: An Improvement on LVQ Algorithms to Create Classes of Patterns. IWANN Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993	B	`conf`	Optimal decision surfaces in LVQ1 classiffication of patterns. ESANN Michel Verleysen, Philippe Thissen, Jean-Didier Legat
1993	C	`conf`	Systolic implementation of a bidimensional lattice filter bank for multiresolution image coding. VCIP Pierre Desneux, Jean-Didier Legat, Benoît Macq, Jean-Yves Mertès
1992	—	`conf`	A real-time VLSI-based architecture for multi-motion estimation. ICPR (4) Jean-Didier Legat, J. P. Cornil, Damien Macq, Michel Verleysen