Jean-Baptiste Rigaud

67 papers A 8B 1C 17Journal 14Unranked 26
YearRankTypeTitle / Venue / Authors
2025 — conf
Betrayed by Light: How Photon Emission Microscopy Empowers Register Bit-Level Laser Attacks on Microcontrollers.
HOST
Hugo Perrin, Jean-Max Dutertre, Jean-Baptiste Rigaud
2025 J jnl
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture.
CoRR
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart, Nils Wistoff, Zexin Fu, Filippo Grillotti, Fabio De Ambroggi, Elio Guidetti, Jean-Baptiste Rigaud, Olivier Potin, Jean-Roch Coulon, César Fuguet, Luca Benini, Davide Rossi
2025 — conf
Code Encryption for Confidentiality and Execution Integrity Down to Control Signals.
HOST
Théophile Gousselot, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud
2025 C conf
Eliminating Write-After-Write Hazards to Improve Performance in Embedded Processors.
DSD
Côme Allart, Junheng Zheng, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud
2024 — conf
Analysis and Mitigation of Hybrid CMOS/MRAM DFF Vulnerabilities to Laser Fault Injection.
AsianHOST
Raphaël Comps, Jean-Baptiste Rigaud, Jean-Max Dutertre
2024 C conf
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design.
IOLTS
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2024 — conf
Using a Performance Model to Implement a Superscalar CVA6.
CF (Companion)
Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud
2024 J jnl
Using a Performance Model to Implement a Superscalar CVA6.
CoRR
Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin, Jean-Baptiste Rigaud
2023 — conf
A CCFI Verification Scheme Based on the RISC-V Trace Encoder.
COSADE
Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre
2023 C conf
A Tale of Two Models: Discussing the Timing and Sampling EM Fault Injection Models.
FDTC
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2023 — conf
CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core.
HOST
Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre
2023 J jnl
Experimental EMFI detection on a RISC-V core using the Trace Verifier solution.
Microprocess. Microsystems
Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre
2023 A conf
Highlighting Two EM Fault Models While Analyzing a Digital Sensor Limitations.
DATE
Roukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage
2023 — conf
Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core.
HOST
Théophile Gousselot, Olivier Thomas, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud
2023 C conf
Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-Bit Microcontrollers.
CARDIS
Raphaël Joud, Pierre-Alain Moëllic, Simon Pontié, Jean-Baptiste Rigaud
2023 J jnl
Like an Open Book? Read Neural Network Architecture with Simple Power Analysis on 32-bit Microcontrollers.
CoRR
Raphaël Joud, Pierre-Alain Moëllic, Simon Pontie, Jean-Baptiste Rigaud
2023 A conf
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation.
DATE
Nathan Roussel, Olivier Potin, Jean-Max Dutertre, Jean-Baptiste Rigaud
2022 C conf
A CFI Verification System based on the RISC-V Instruction Trace Encoder.
DSD
Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre
2022 C conf
A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters.
CARDIS
Raphaël Joud, Pierre-Alain Moëllic, Simon Pontié, Jean-Baptiste Rigaud
2022 J jnl
A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters.
CoRR
Raphaël Joud, Pierre-Alain Moëllic, Simon Pontie, Jean-Baptiste Rigaud
2022 C conf
An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation.
IOLTS
William Souza da Cruz, Raphael Viera, Jean-Baptiste Rigaud, Guillaume Hubert, Jean-Max Dutertre
2022 — conf
CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation.
ICECS 2022
Nathan Roussel, Olivier Potin, Gregory di Pendina, Jean-Max Dutertre, Jean-Baptiste Rigaud
2021 — conf
A Review of Confidentiality Threats Against Embedded Neural Network Models.
WF-IoT
Raphaël Joud, Pierre-Alain Moëllic, Rémi Bernhard, Jean-Baptiste Rigaud
2021 J jnl
A Review of Confidentiality Threats Against Embedded Neural Network Models.
CoRR
Raphaël Joud, Pierre-Alain Moëllic, Rémi Bernhard, Jean-Baptiste Rigaud
2021 — conf
Further Analysis of Laser-induced IR-drop.
ATS
William Souza da Cruz, Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert
2021 — conf
Hardware Implementation of Multiplication over Quartic Extension Fields.
ICMC
Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud
2021 C conf
Hardware Implementations of Pairings at Updated Security Levels.
CARDIS
Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud, Julien Proy
2020 — conf
Evidence of a Dynamic Fault Model in the DICE Radiation-Hardened Cell.
SBCCI
William Souza da Cruz, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert
2020 — conf
Experimental Analysis of the Electromagnetic Instruction Skip Fault Model.
DTIS
Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud, Jean-Luc Danger
2020 J jnl
Multiplication over Extension Fields for Pairing-based Cryptography: an Hardware Point of View.
IACR Cryptol. ePrint Arch.
Arthur Lavice, Nadia El Mrabet, Alexandre Berzati, Jean-Baptiste Rigaud
2020 C conf
Single-bit Laser Fault Model in NOR Flash Memories: Analysis and Exploitation.
FDTC
Alexandre Menu, Jean-Max Dutertre, Jean-Baptiste Rigaud, Brice Colombier, Pierre-Alain Moëllic, Jean-Luc Danger
2019 — conf
Experimental Analysis of the Laser-Induced Instruction Skip Fault Model.
NordSec
Jean-Max Dutertre, Timothée Riom, Olivier Potin, Jean-Baptiste Rigaud
2019 — conf
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller.
HOST
Brice Colombier, Alexandre Menu, Jean-Max Dutertre, Pierre-Alain Moëllic, Jean-Baptiste Rigaud, Jean-Luc Danger
2019 C conf
Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers.
FDTC
Alexandre Menu, Shivam Bhasin, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger
2018 J jnl
Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller.
IACR Cryptol. ePrint Arch.
Brice Colombier, Alexandre Menu, Jean-Max Dutertre, Pierre-Alain Moëllic, Jean-Baptiste Rigaud, Jean-Luc Danger
2017 J jnl
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs.
J. Hardw. Syst. Secur.
Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout
2016 — conf
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs.
SPACE
Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout
2016 J jnl
A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems.
IACR Cryptol. ePrint Arch.
Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout
2016 A conf
A fully-digital EM pulse detector.
DATE
David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine
2016 C conf
An Embedded Digital Sensor against EM and BB Fault Injection.
FDTC
David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine
2016 — conf
Body Biasing Injection Attacks in Practice.
CS2@HiPEAC
Noemie Beringuier-Boher, Marc Lacruche, David El-Baze, Jean-Max Dutertre, Jean-Baptiste Rigaud, Philippe Maurine
2016 C conf
High-Performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication.
CRiSIS
Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout
2016 A conf
On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults.
DATE
Marc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud, Edith Kussener
2015 — conf
Evidence of an information leakage between logically independent blocks.
CS2@HiPEAC
Loïc Zussa, Ingrid Exurville, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria, Jessy Clédière
2015 A conf
Hardware trojan detection by delay and electromagnetic measurements.
DATE
Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson
2015 C conf
Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses.
IOLTS
Marc Lacruche, Nicolas Borrel, Clement Champeix, Cyril Roscian, Alexandre Sarafianos, Jean-Baptiste Rigaud, Jean-Max Dutertre, Edith Kussener
2015 — conf
Resilient hardware Trojans detection based on path delay measurements.
HOST
Ingrid Exurville, Loïc Zussa, Jean-Baptiste Rigaud, Bruno Robisson
2014 J jnl
Analysis Of Variance and CPA in SCA.
IACR Cryptol. ePrint Arch.
Sébastien Tiran, Guillaume Reymond, Jean-Baptiste Rigaud, Driss Aboulkassimi, Benedikt Gierlichs, Mathieu Carbone, Gilles R. Ducharme, Philippe Maurine
2014 — conf
Detecting positive voltage attacks on CMOS circuits.
CS2@HiPEAC
Kamil Gomina, Philippe Gendrier, Philippe Candelier, Jean-Baptiste Rigaud, Assia Tria
2014 — conf
Power supply glitch attacks: Design and evaluation of detection circuits.
HOST
Kamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Philippe Candelier, Assia Tria
2014 C conf
Voltage Glitch Attacks on Mixed-Signal Systems.
DSD
Noemie Beringuier-Boher, Kamil Gomina, David Hély, Jean-Baptiste Rigaud, Vincent Beroulle, Assia Tria, Joel Damiens, Philippe Gendrier, Philippe Candelier
2013 C conf
Power analysis methodology for secure circuits.
DDECS
Kamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Philippe Candelier, Assia Tria
2011 — conf
A side-channel and fault-attack resistant AES circuit working on duplicated complemented values.
ISSCC
Marion Doulcier-Verdier, Jean-Max Dutertre, Jacques J. A. Fournier, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria
2011 J jnl
Design and characterisation of an AES chip embedding countermeasures.
Int. J. Intell. Eng. Informatics
Jacques J. A. Fournier, Jean-Baptiste Rigaud, Sylvain Bouquet, Bruno Robisson, Assia Tria, Jean-Max Dutertre, Michel Agoyan
2010 — conf
Experimental Fault Injection based on the Prototyping of an AES Cryptosystem.
ReCoSoC
Jean-Baptiste Rigaud, Jean-Max Dutertre, Michel Agoyan, Bruno Robisson, Assia Tria
2008 C conf
Error Detection for Borrow-Save Adders Dedicated to ECC Unit.
FDTC
Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand
2007 A conf
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling.
DATE
Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria
2007 J jnl
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
CoRR
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
2007 J jnl
Strengthening hardware AES implementations against fault attacks.
IET Inf. Secur.
Marc Joye, Pascal Manet, Jean-Baptiste Rigaud
2006 — conf
Integrated Evaluation Platform for Secured Devices.
ReCoSoC
Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi
2005 A conf
Hardware Engines for Bus Encryption: A Survey of Existing Techniques.
DATE
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
2003 — conf
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.
HICSS
Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani
2003 — conf
Statistic Implementation of QDI Asynchronous Primitives.
PATMOS
Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
2002 A conf
High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.
DATE
Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
2002 B conf
Implementing Asynchronous Circuits on LUT Based FPGAs.
FPL
Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
2002 — —
Spécification de bibliothèques pour la synthèse de circuits asynchrones. (Libraries specification for the synthesis of asynchronous circuits).
Jean-Baptiste Rigaud
2001 C conf
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.
VLSI-SOC
Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin