Jaynarayan T. Tudu

32 papers B 3C 4Misc 1Journal 2Unranked 21
YearRankTypeTitle / Venue / Authors
2026 — conf
SCALER: Sensitivity-Centric Adaptive Layer Execution & Runtime Mapping for Hybrid Analog-Digital Accelerator.
EuroMLSys@EuroSys
Naman Kalra, Bonthu Purna Nand, Jaynarayan T. Tudu
2025 — conf
Distant History Branch Prediction Using Advanced Machine Learning Techniques.
HiPCW
Bonthu Purnanand, Jaynarayan T. Tudu
2025 — conf
RL-Driven Fine-Grained Power Gating for Modern Processors Using Multi-Layer Perceptron Models.
ISQED
Naman Kalra, Jaynarayan T. Tudu
2025 B conf
SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality Analysis.
ETS
Haripriya R. S, Naveen Kollepara, Jaynarayan T. Tudu
2024 — conf
AI-Driven Power Gating for Enhanced Energy Efficiency in Superscalar Processors.
HIPCW
Naman Kalra, Jaynarayan T. Tudu
2024 Misc conf
Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing.
VLSID
Haripriya R. S, Soumitro Vyapari, Jaynarayan T. Tudu
2024 — conf
Physical-Design Aware Scan Cell Reordering for Low Power Testing.
EWDTS
Rohit Badjatya, N. S. Vinay, Rahul Kumar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2022 J jnl
Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption.
CoRR
Lakshmi Bhanuprakash Reddy Konduru, Vijaya Lakshmi, Jaynarayan T. Tudu
2022 — conf
On Protecting IJTAG from Data Sniffing and Alteration Attacks.
ISVLSI
Anjum Riaz, Gaurav Kumar, Jaynarayan T. Tudu, Satyadev Ahlawat
2022 — ed.
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers
VDAT
Ambika Prasad Shah, Sudeb Dasgupta, Anand D. Darji, Jaynarayan T. Tudu
2021 J jnl
A Framework for Configurable Joint-Scan Design-for-Test Architecture.
J. Electron. Test.
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh
2020 — conf
LUT-based Circuit Approximation with Targeted Error Guarantees.
ATS
Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2019 — conf
Preventing Scan Attack through Test Response Encryption.
DFT
Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh
2019 C conf
Securing Scan through Plain-text Restriction.
IOLTS
Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2018 C conf
On Securing Scan Design Through Test Vector Encryption.
ISCAS
Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
2017 — conf
A Cost Effective Technique for Diagnosis of Scan Chain Faults.
VDAT
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag
2017 — conf
On Securing Scan Design from Scan-Based Side-Channel Attacks.
ATS
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh
2017 C conf
Revisiting random access scan for effective enhancement of post-silicon observability.
IOLTS
Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh
2016 C conf
A high performance scan flip-flop design for serial and mixed mode scan test.
IOLTS
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2016 — conf
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture.
EWDTS
Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu
2016 — conf
Guided shifting of test pattern to minimize test time in serial scan.
VDAT
Jaynarayan T. Tudu, Satyadev Ahlawat
2016 — conf
JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power.
VDAT
Jaynarayan T. Tudu
2016 — conf
On determination of instantaneous peak and cycle peak switching using ILP.
VDAT
Rohini Gulve, Nihar Hage, Jaynarayan T. Tudu
2016 — conf
On minimization of test power through modified scan flip-flop.
VDAT
Satyadev Ahlawat, Jaynarayan T. Tudu
2016 — conf
Skip-scan: A methodology for test time reduction.
VDAT
Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu
2015 — conf
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan.
ATS
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
2013 — conf
Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP.
VDAT
Jaynarayan T. Tudu, Deepak Malani, Virendra Singh
2012 — conf
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits.
VDAT
Jaynarayan T. Tudu, Deepak Malani, Virendra Singh
2010 — conf
Graph theoretic approach for scan cell reordering to minimize peak shift power.
ACM Great Lakes Symposium on VLSI
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010 — conf
On selection of state variables for delay test of identical functional units.
EWDTS
Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan T. Tudu, Virendra Singh
2010 B conf
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.
ETS
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2009 B conf
On Minimization of Peak Power for Scan Circuit during Test.
ETS
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal