Jaydeep P. Kulkarni

105 papers A* 8A 6C 4Misc 2Journal 37Unranked 48
YearRankTypeTitle / Venue / Authors
2026 J jnl
ABI: A tightly integrated, unified, sparsity-aware, reconfigurable, compute near-register file/cache GPU architecture with light-weight softmax for deep learning, linear algebra, and Ising compute.
CoRR
Siddhartha Raman Sundara Raman, Jaydeep P. Kulkarni
2026 A conf
MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage.
FPGA
Tarun Kholay, Anup Ashok Kedilaya, Aman Arora, Jaydeep P. Kulkarni, Lizy K. John
2025 C conf
3D IGZO Charge-Coupled Memory DTCO & STCO Analysis for Compute-near-Memory Applications.
ISCAS
Bowen Wang, Khakim Akhunov, Hyungrock Oh, Fernando García-Redondo, Yukai Chen, Arvind Sharma, Jiacong Sun, Sahan Gamage, Maarten Rosmeulen, Swaraj Bandhu Mahato, Rishabh Kishore, Subhali Subhechha, Jaydeep P. Kulkarni, Marian Verhelst, Dwaipayan Biswas, Marie Garcia Bardon, Wim Dehaene, Julien Ryckaert
2025 C conf
3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology.
ISCAS
Bhawana Kumari, Anurag Swarnkar, Dawit Burusie Abdi, Fernando García-Redondo, James Myers, Julien Ryckaert, Jaydeep P. Kulkarni, Dwaipayan Biswas
2025 J jnl
A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology.
IEEE Solid State Circuits Lett.
Kedar Bhatt, Stafford Hutchins, Atresh Sanne, Mohammad M. Hasan, Zhanping Chen, Jaydeep P. Kulkarni
2025 — conf
Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications.
IMW
Anurag Swarnkar, Dawit Burusie Abdi, Bhawana Kumari, Priya Venugopal, Nicolas Pantano, Geert Hellings, Jaydeep P. Kulkarni, Dwaipayan Biswas, Julien Ryckaert, Fernando García-Redondo
2025 A* conf
GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-centric Rasterization.
DAC
Mengtian Yang, Yipeng Wang, Chieh-Pu Lo, Xiuhao Zhang, Sirish Oruganti, Jaydeep P. Kulkarni
2025 — conf
Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection.
IRPS
Sizhe Ma, Saikat Chakraborty, Yixin Qin, Zijian Zhao, Jiahui Duan, Moonyoung Jung, Kijoon Kim, Suhwan Lim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, Kai Ni
2025 — conf
Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology.
ISPD
Meizhi Wang, Yi-Ru Chen, S. S. Teja Nibhanupudi, Elham Amini, Antonio Saavedra, Yinan Wang, Daniel Wasserman, Jean-Pierre Seifert, Jaydeep P. Kulkarni
2025 — conf
Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage.
IRPS
Yixin Qin, Saikat Chakraborty, Zijian Zhao, Sizhe Ma, Moonyoung Jung, Kijoon Kim, Suhwan Lim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni, Kai Ni
2025 A* conf
SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory Architecture for Accelerating Linear Programming Problems.
HPCA
Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni
2025 J jnl
Unconventional Computing Using Ising Accelerators.
Computer
Jaydeep P. Kulkarni, Siddhartha Raman Sundara Raman, Shanshan Xie, Chieh-Pu Lo
2025 J jnl
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training.
CoRR
Yipeng Wang, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni
2024 — conf
30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing.
ISSCC
Yipeng Wang, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni
2024 — conf
Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers.
DRC
Juhan Ahn, Saroj Satapathy, Jaydeep P. Kulkarni
2024 — conf
Analyzing the Dynamics of Store Mechanism and Data Retention through Transient Simulations in Si/Ge TRAM for Cryogenic Memory Applications.
DRC
Saikat Chakraborty, Jaydeep P. Kulkarni
2024 — conf
CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems.
CICC
Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni
2024 J jnl
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks.
ACM Trans. Archit. Code Optim.
Siddhartha Raman Sundara Raman, Lizy Kurian John, Jaydeep P. Kulkarni
2024 — conf
Power and EM Side-Channel-Attack-Resilient AES-128 Core with Round-Aligned Globally-Synchronous-Locally-Asynchronous Operation Based on Tunable Replica Circuits.
ISSCC
Sirish Oruganti, Meizhi Wang, Vishnuvardhan V. Iyer, Yipeng Wang, Mengtian Yang, Raghavan Kumar, Sanu K. Mathew, Jaydeep P. Kulkarni
2024 — conf
Randomization Approaches for Secure SAR ADC Design Resilient Against Power Side-Channel Attacks.
HOST
Sumanth N. Karanth, Sirish Oruganti, Meizhi Wang, Jaydeep P. Kulkarni
2024 A* conf
SACHI: A Stationarity-Aware, All-Digital, Near-Memory, Ising Architecture.
HPCA
Siddhartha Raman Sundara Raman, Lizy K. John, Jaydeep P. Kulkarni
2024 J jnl
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters.
IEEE J. Solid State Circuits
Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
2023 Misc conf
A 118 GOPS/mm
HiPC
Mengtian Yang, Yipeng Wang, Jaydeep P. Kulkarni
2023 J jnl
A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits
Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni
2023 — conf
A GNN Computing-in-Memory Macro and Accelerator with Analog-Digital Hybrid Transformation and CAMenabled Search-reduce.
CICC
Yipeng Wang, Shanshan Xie, Jacob N. Rohan, Meizhi Wang, Mengtian Yang, Sirish Oruganti, Jaydeep P. Kulkarni
2023 J jnl
An Estimator for the Sensitivity to Perturbations of Deep Neural Networks.
CoRR
Naman Maheshwari, Nicholas Malaya, Scott Moe, Jaydeep P. Kulkarni, Sudhanva Gurumurthi
2023 J jnl
An In-Memory-Computing Charge-Domain Ternary CNN Classifier.
IEEE J. Solid State Circuits
Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2023 — conf
CIMGN: An Energy-efficient All-digital Compute-in-memory Graph Neural Network Processor.
ESSCIRC
Yipeng Wang, Mengtian Yang, Shanshan Xie, Meizhi Wang, Jaydeep P. Kulkarni
2023 J jnl
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration.
ACM Trans. Reconfigurable Technol. Syst.
Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep P. Kulkarni, Lizy K. John
2023 — conf
Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines.
ESSCIRC
Rishabh Sehgal, Rishab Mehra, Can Ni, Jaydeep P. Kulkarni
2023 A* conf
Invited: Buried Power Rails and Back-side Power Grids: Prospects and Challenges.
DAC
S. S. Teja Nibhanupudi, Sirish Oruganti, Rahul Mathur, Nishant Gupta, Meizhi Wang, Jaydeep P. Kulkarni
2023 — conf
Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for Large-Scale Hard Boolean Satisfiability Problems.
ISSCC
Shanshan Xie, Mengtian Yang, S. Andrew Lanham, Yipeng Wang, Meizhi Wang, Sirish Oruganti, Jaydeep P. Kulkarni
2022 — conf
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.
VLSI Technology and Circuits
Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
2022 — conf
Aging Effects On Clock Gated Memory Phase Paths.
DFT
Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi
2022 J jnl
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim
2022 — conf
Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM.
DRC
Saikat Chakraborty, Jaydeep P. Kulkarni
2022 Misc conf
CoMeFa: Compute-in-Memory Blocks for FPGAs.
FCCM
Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep P. Kulkarni, Lizy K. John
2022 J jnl
CoMeFa: Compute-in-Memory Blocks for FPGAs.
CoRR
Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep P. Kulkarni, Lizy K. John
2022 — conf
Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing.
DRC
Saikat Chakraborty, Jaydeep P. Kulkarni
2022 J jnl
Enabling In-Memory Computations in Non-Volatile SRAM Designs.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Siddhartha Raman Sundara Raman, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
2022 — conf
Experimental demonstration of sub-nanosecond switching in 2D hexagonal Boron Nitride resistive memory devices.
DRC
S. S. Teja Nibhanupudi, Dmitry Veksler, Anupam Roy, Matthew Coupin, Kevin C. Matthews, Jamie Warner, Gennadi Bersuker, Jaydeep P. Kulkarni, Sanjay Kumar Banerjee
2022 — conf
Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks.
ESSCIRC
Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni
2022 — conf
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.
VLSI Technology and Circuits
Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
2022 J jnl
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Tony Tae-Hyoung Kim, Bongjin Kim, Joo-Young Kim, Jaydeep P. Kulkarni
2022 J jnl
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits
Shanshan Xie, Siddhartha Raman Sundara Raman, Can Ni, Meizhi Wang, Mengtian Yang, Jaydeep P. Kulkarni
2022 — conf
Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.
DRC
Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
2021 — conf
16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.
ISSCC
Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni
2021 — conf
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.
CICC
Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni
2021 C conf
A Systematic Evaluation of EM and Power Side-Channel Analysis Attacks on AES Implementations.
ISI
Vishnuvardhan V. Iyer, Meizhi Wang, Jaydeep P. Kulkarni, Ali E. Yilmaz
2021 — conf
An In-Memory-Computing Charge-Domain Ternary CNN Classifier.
CICC
Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun
2021 J jnl
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing.
IEEE J. Solid State Circuits
Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
2021 C conf
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors.
ISCAS
Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni
2021 — conf
Field-Emission Enhanced Contacts for Disordered Semiconductor based Thin-Film Transistors.
DRC
Kelly Liang, Xiao Wang, Yuchen Zhou, Xin Xu, Calla McCulley, Liang Wang, Jaydeep P. Kulkarni, Ananth Dodabalapur
2021 — conf
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management.
CICC
Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
2021 — conf
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.
CICC
Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
2021 — conf
Realizing Direct Convolution in Memory with Systolic-RAM.
A-SSCC
Jacob N. Rohan, Jaydeep P. Kulkarni
2021 — conf
Trends in Analog and Digital Intensive Compute-in-SRAM Designs.
AICAS
Rishabh Sehgal, Jaydeep P. Kulkarni
2020 J jnl
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing.
IEEE J. Solid State Circuits
Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni
2020 J jnl
Chip Design 2020.
IEEE Micro
Jaydeep P. Kulkarni
2020 — conf
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.
VLSI Circuits
Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
2020 J jnl
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aseem Sayal, Paras Ajay, Mark W. McDermott, S. V. Sreenivasan, Jaydeep P. Kulkarni
2020 J jnl
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology.
CoRR
Rahul Mathur, Chien-Ju Chao, Rossana Liu, Nikhil Tadepalli, Pranavi Chandupatla, Shawn Hung, Xiaoqing Xu, Saurabh Sinha, Jaydeep P. Kulkarni
2019 — conf
All-Digital Time-Domain CNN Engine Using Bidirectional Memory Delay Lines for Energy-Efficient Edge Computing.
ISSCC
Aseem Sayal, Shirin Fathima, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni
2019 J jnl
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 — conf
Neural Network Assisted Compact Model for Accurate Characterization of Cycle-to-cycle Variations in 2-D $h$-BN based RRAM devices.
DRC
Jacob N. Rohan, Pingping Zhuang, S. S. Teja Nibhanupudi, Sanjay Kumar Banerjee, Jaydeep P. Kulkarni
2018 — conf
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
ISSCC
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018 J jnl
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst.
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni
2018 J jnl
Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design.
IEEE Des. Test
Jaydeep P. Kulkarni, Thomas F. Wenisch
2018 A* conf
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation.
DAC
Subrahmanya Teja, Jaydeep P. Kulkarni
2018 J jnl
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni
2017 J jnl
5.6 Mb/mm
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2017 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017 A conf
Message from the program co-chairs.
ISLPED
Jaydeep P. Kulkarni, Thomas F. Wenisch
2017 J jnl
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.
IEEE J. Solid State Circuits
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016 — conf
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
ISSCC
John Keane, Jaydeep P. Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
2016 — conf
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.
ISSCC
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2016 J jnl
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging.
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2016 J jnl
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015 — conf
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.
ISSCC
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
2015 — conf
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
ISSCC
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015 A conf
A novel slope detection technique for robust STTRAM sensing.
ISLPED
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep P. Kulkarni
2014 — conf
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
ISSCC
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014 J jnl
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep P. Kulkarni, James W. Tschanz, Vivek De
2013 A* conf
Improving multi-core performance using mixed-cell cache architecture.
HPCA
Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep P. Kulkarni, Daniel A. Jiménez
2012 — conf
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
ISSCC
Jaydeep P. Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De
2012 A conf
Design for test and reliability in ultimate CMOS.
DATE
Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012 J jnl
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.
IEEE Trans. Very Large Scale Integr. Syst.
Jaydeep P. Kulkarni, Kaushik Roy
2011 J jnl
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.
IEEE Trans. Very Large Scale Integr. Syst.
Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy
2011 — conf
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.
NANOARCH
Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, Jaydeep P. Kulkarni
2010 — conf
Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit.
ISSCC
Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy
2010 J jnl
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
2010 J jnl
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
2010 — conf
Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.
CICC
Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep P. Kulkarni, Tanay Karnik, Vivek De
2010 — conf
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
ISSCC
Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010 — conf
Resilient design in scaled CMOS for energy efficiency.
ASP-DAC
James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2009 A* conf
Device/circuit interactions at 22nm technology node.
DAC
Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta
2009 — conf
REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN.
CICC
Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy
2008 — conf
A high sensitivity process variation sensor utilizing sub-threshold operation.
CICC
Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
2008 A* conf
Process variation tolerant SRAM array for ultra low voltage applications.
DAC
Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy
2008 A conf
Thermal analysis of 8-T SRAM for nano-scaled technologies.
ISLPED
Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
2007 J jnl
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM.
IEEE J. Solid State Circuits
Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
2007 A conf
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.
ISLPED
Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
2007 — conf
A High Performance, Scalable Multiplexed Keeper Technique.
ISQED
Jaydeep P. Kulkarni, Kaushik Roy
2004 J jnl
A Fast LSF Search Algorithm Based on Interframe Correlation in G.723.1.
EURASIP J. Adv. Signal Process.
Sameer A. Kibey, Jaydeep P. Kulkarni, Piyush D. Sarode