Jayaram Bhasker

15 papers A* 3A 1Journal 9Unranked 1
YearRankTypeTitle / Venue / Authors
2004 A conf
Improving Design and Verification Productivity with VHDL-200x.
DATE
Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden
1996 — book
Die VHDL-Syntax.
Jayaram Bhasker
1995 J jnl
Datapath synthesis using a problem-space genetic algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker
1994 J jnl
Size, chromatic number, and connectivity.
Graphs Comb.
Jayaram Bhasker, Tariq Samad, Douglas B. West
1991 J jnl
Simulation-Based Verification for High-Level Synthesis.
IEEE Des. Test Comput.
Rolf Ernst, Jayaram Bhasker
1990 J jnl
An Optimizer for Hardware Synthesis.
IEEE Des. Test Comput.
Jayaram Bhasker, Huan-Chih Lee
1989 J jnl
Via Assignment in Single-Row Routing.
IEEE Trans. Computers
Jayaram Bhasker, Sartaj Sahni
1988 J jnl
A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph.
Algorithmica
Jayaram Bhasker, Sartaj Sahni
1988 J jnl
Implementation of an optimizing compiler for VHDL.
ACM SIGPLAN Notices
Jayaram Bhasker
1988 J jnl
Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis.
Softw. Pract. Exp.
Jayaram Bhasker
1987 J jnl
A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graph.
Networks
Jayaram Bhasker, Sartaj Sahni
1987 A* conf
An algorithm for microcode compaction of VHDL behavioral descriptions.
MICRO
Jayaram Bhasker
1987 A* conf
Compacting MIMOLA microcode.
MICRO
Jayaram Bhasker, Tariq Samad
1986 A* conf
A linear algorithm to find a rectangular dual of a planar triangulated graph.
DAC
Jayaram Bhasker, Sartaj Sahni
1986 — conf
Via Assignment in Single Row Routing.
FSTTCS
Jayaram Bhasker, Sartaj Sahni