Jayanta Bhadra

54 papers A* 2A 12B 1C 1Misc 6Journal 11Unranked 19

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Practices and Challenges for Achieving Functional Safety of Modern Automotive SoCs. IEEE Des. Test Wen Chen, Jayanta Bhadra
2017	J	`jnl`	Challenges and Trends in Modern SoC Design Verification. IEEE Des. Test Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
2017	J	`jnl`	Data-Driven Test Plan Augmentation for Platform Verification. IEEE Des. Test Wen Chen, Kuo-Kai Hsieh, Li-Chung Wang, Jayanta Bhadra
2017	A*	`conf`	Extensibility in Automotive Security: Current Practice and Challenges: Invited. DAC Sandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque
2017	—	`conf`	Feature extraction from design documents to enable rule learning for improving assertion coverage. ASP-DAC Kuo-Kai Hsieh, Sebastian Siatkowski, Li-C. Wang, Wen Chen, Jayanta Bhadra
2017	J	`jnl`	Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification. IEEE Des. Test Magdy S. Abadir, Jayanta Bhadra, Wen Chen, Li-C. Wang
2017	A*	`conf`	Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery. DAC Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra
2016	—	`conf`	Security challenges in mobile and IoT systems. SoCC Sandip Ray, Jayanta Bhadra
2016	—	`conf`	Striking a balance between SoC security and debug requirements. SoCC Wen Chen, Jayanta Bhadra
2014	A	`conf`	On application of data mining in functional debug. ICCAD Kuo-Kai Hsieh, Wen Chen, Li-C. Wang, Jayanta Bhadra
2013	—	`conf`	Novel test analysis to improve structural coverage - A commercial experiment. VLSI-DAT Wen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir
2013	A	`conf`	Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step. DATE Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra
2012	—	`conf`	An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ASP-DAC Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra
2012	J	`jnl`	Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta
2012	A	`conf`	Novel test detection to improve simulation efficiency - A commercial experiment. ICCAD Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir
2011	—	`conf`	A Unified Formal Framework for Analyzing Functional and Speed-path Properties. MTV Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula
2010	A	`conf`	A kernel-based approach for functional test program generation. ITC Po-Hsien Chang, Li-C. Wang, Jayanta Bhadra
2010	Misc	`conf`	Innovative practices session 7C: Verification and testing challenges in high-level synthesis. VTS Sandip Ray, Jayanta Bhadra
2010	—	`conf`	Modeling and verification of industrial flash memories. ISQED Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek
2009	—	`conf`	Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra
2009	—	`conf`	An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller
2009	A	`conf`	On soft error rate analysis of scaled CMOS designs - A statistical perspective. ICCAD Huan-Kai Peng, Charles H.-P. Wen, Jayanta Bhadra
2009	A	`conf`	Portable simulation/emulation stimulus on an industrial-strength SoC. ITC Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra
2009	—	`conf`	Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. MTV Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra
2009	A	`conf`	Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning. ITC Chia-Ling Chang, Charles H.-P. Wen, Jayanta Bhadra
2009	—	`conf`	Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. ISVLSI Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra
2008	J	`jnl`	Validating Power Architecture IEEE Trans. Very Large Scale Integr. Syst. Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir
2007	B	`conf`	A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD Sandip Ray, Jayanta Bhadra
2007	J	`jnl`	A Survey of Hybrid Techniques for Functional Verification. IEEE Des. Test Comput. Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray
2007	A	`conf`	An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra
2007	—	`ed.`	Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA MTV Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra
2007	A	`conf`	Enhancing signal controllability in functional test-benches through automatic constraint extraction. ITC Onur Guzey, Li-C. Wang, Jayanta Bhadra
2007	J	`jnl`	Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Des. Test Comput. Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang
2006	—	`conf`	A Trace-Driven Validation Methodology for Multi-Processor SOCS. SoCC Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir
2006	—	`conf`	Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
2006	—	`ed.`	Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA MTV Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra
2005	J	`jnl`	A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods Syst. Des. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham
2005	—	`conf`	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova
2005	—	`conf`	Establishing latch correspondence for embedded circuits of PowerPC microprocessors. HLDVT Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis
2004	J	`jnl`	Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Des. Test Comput. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
2004	A	`conf`	Formal Verification of a System-on-Chip Using Computation Slicing. ITC Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra
2004	Misc	`conf`	Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2003	J	`jnl`	A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electron. Test. Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri
2003	—	`conf`	A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
2003	Misc	`conf`	Model Checking of Security Protocols with Pre-configuration. WISA Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra
2002	A	`conf`	Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. ITC Jayanta Bhadra, Narayanan Krishnamurthy
2002	Misc	`conf`	Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2002	Misc	`conf`	Program Slicing for Hierarchical Test Generation. VTS Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
2001	—	`conf`	A language formalism for verification of PowerPC HLDVT Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2001	A	`conf`	Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
2001	—	`conf`	Using Abstract Specifications to Verify PowerPC CHARME Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
2000	—	`conf`	A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC CICC Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
2000	Misc	`conf`	Automatic Validation Test Generation Using Extracted Control Models. VLSI Design Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
1999	C	`conf`	Improving Witness Search Using Orders on States. ICCD Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham