Jayanand Asok Kumar

12 papers A* 2A 2B 1Misc 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2014 J jnl
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jayanand Asok Kumar, Seyed Nematollah Ahmadyan, Shobha Vasudevan
2013 J jnl
Formal Probabilistic Timing Verification in RTL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jayanand Asok Kumar, Shobha Vasudevan
2013 A conf
Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm.
DATE
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
2012 A* conf
Early prediction of NBTI effects using RTL source code analysis.
DAC
Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan
2012 J jnl
Formal Performance Analysis for Faulty MIMO Hardware.
IEEE Trans. Very Large Scale Integr. Syst.
Jayanand Asok Kumar, Shobha Vasudevan
2012 A* conf
Goal-oriented stimulus generation for analog circuits.
DAC
Seyed Nematollah Ahmadyan, Jayanand Asok Kumar, Shobha Vasudevan
2012 — —
Statistical guarantees of performance for RTL designs
Jayanand Asok Kumar
2012 — conf
Verifying dynamic power management schemes using statistical model checking.
ASP-DAC
Jayanand Asok Kumar, Shobha Vasudevan
2011 B conf
Scaling probabilistic timing verification of hardware using abstractions in design source code.
FMCAD
Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan
2011 Misc conf
Variation-Conscious Formal Timing Verification in RTL.
VLSI Design
Jayanand Asok Kumar, Shobha Vasudevan
2010 — conf
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs.
QEST
Jayanand Asok Kumar, Shobha Vasudevan
2010 A conf
Statistical guarantees of performance for MIMO designs.
DSN
Jayanand Asok Kumar, Shobha Vasudevan