Jawahar Jain - RankMe

47 papers A* 6A 6B 4C 1Misc 9Journal 6Unranked 15

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	Comparing stress markers across various cohorts in a mobile setting. EMBC Shreyans Gandhi, Jawahar Jain, Maryam Shojaei Baghini, Soumyo Mukherji
2013	A	`conf`	Optimizing BDDs for time-series dataset manipulation. DATE Stergios Stergiou, Jawahar Jain
2010	—	`conf`	Dynamically resizable binary decision diagrams. ACM Great Lakes Symposium on VLSI Stergios Stergiou, Jawahar Jain
2008	—	`conf`	Optimizing routing tables on systems-on-chip with Content-Addressable Memories. SoC Stergios Stergiou, Jawahar Jain
2006	—	`conf`	Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. HLDVT Stergios Stergiou, Jawahar Jain
2006	J	`jnl`	On partitioning and symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
2005	B	`conf`	A New Reachability Algorithm for Symmetric Multi-processor Architecture. ATVA Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
2005	—	`conf`	Error Detection Using BMC in a Parallel Environment. CHARME Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
2005	A*	`conf`	Multi-threaded reachability. DAC Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
2005	B	`conf`	On Partitioning and Symbolic Model Checking. FM Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
2005	—	`conf`	Predictive Reachability Using a Sample-Based Approach. CHARME Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
2005	—	`conf`	Under-approximation Heuristics for Grid-based Bounded Model Checking. PDMC@ICALP Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson
2005	—	`conf`	Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. Asian Test Symposium Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu
2004	B	`conf`	A Partitioning Methodology for BDD-Based Verification. FMCAD Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
2004	Misc	`conf`	Can SAT be used to Improve Sequential ATPG Methods? VLSI Design Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
2003	—	`conf`	Improved Symbolic Verification Using Partitioning Techniques. CHARME Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
2003	A*	`conf`	Solving the latch mapping problem in an industrial setting. DAC Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain
2002	J	`jnl`	Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
2002	—	`conf`	Improving Sequential ATPG Using SAT Methods. IWLS Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
2001	J	`jnl`	A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers Jawahar Jain, Ingo Wegener, Masahiro Fujita
2001	—	`conf`	Practical use of sequential ATPG for model checking: going the extra mile does pay off. HLDVT Michael S. Hsiao, Jawahar Jain
2000	A*	`conf`	Analysis of composition complexity and how to obtain smaller canonical graphs. DAC Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu
2000	—	`conf`	Automatic partitioning for efficient combinatorial verification. ASP-DAC Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
2000	A*	`conf`	Efficient variable ordering using aBDD based sampling. DAC Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita
2000	Misc	`conf`	Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
2000	Misc	`conf`	Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
1999	A	`conf`	An Efficient Filter-Based Approach for Combinational Verification. DATE Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999	J	`jnl`	An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1999	Misc	`conf`	Efficient Scheduling Techniques for ROBDD Construction. VLSI Design Rajeev Murgai, Jawahar Jain, Masahiro Fujita
1999	A*	`conf`	Multiple Error Diagnosis Based on Xlists. DAC Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
1998	A	`conf`	Sampling schemes for computing OBDD variable orderings. ICCAD Jawahar Jain, William Adams, Masahiro Fujita
1997	C	`conf`	A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	Misc	`conf`	Formal Verification of Combinational Circuit. VLSI Design Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1997	J	`jnl`	Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1997	A	`conf`	Reachability analysis using partitioned-ROBDDs. ICCAD Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	Misc	`conf`	A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Decomposition Techniques for Efficient ROBDD Construction. FMCAD Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
1996	Misc	`conf`	On More Efficient Combinational ATPG Using Functional Learning. VLSI Design Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
1996	A	`conf`	Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	Advanced Verification Techniques Based on Learning. DAC Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
1995	Misc	`conf`	Efficient variable ordering and partial representation algorithm. VLSI Design Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
1995	—	`conf`	VERIFUL: VERIfication using FUnctional Learning. ED&TC Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
1994	—	`conf`	A new scheme to compute variable orders for binary decision diagrams. Great Lakes Symposium on VLSI Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell
1994	—	`conf`	Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
1994	Misc	`conf`	Functional learning: a new approach to learning in digital circuits. VTS Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan
1992	J	`jnl`	Probabilistic Verification of Boolean Functions. Formal Methods Syst. Des. Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell
1991	A	`conf`	Probabilistic Design Verification. ICCAD Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham