Javier Valls

77 papers A 1B 6C 3Misc 1Journal 45Unranked 21
YearRankTypeTitle / Venue / Authors
2024 J jnl
Acoustic detection of the effects of prolonged fasting on newly hatched broiler chickens.
Comput. Electron. Agric.
Gerardo José Ginovart-Panisello, Ignasi Iriondo, Tesa Panisello Monjo, Silvia Riva, Rodrigo Garcia, Javier Valls, Rosa Maria Alsina Pages
2024 J jnl
Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes.
Quantum
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
2024 — conf
Hybrid POF-VLC Network Downlink in Indoor Environments.
VCC
Pau Salvador, Ma José Canet, Javier Valls, Vicenç Almenar, Juan Luis Corral
2023 — conf
Layered Decoding of Quantum LDPC Codes.
ISTC
Julien du Crest, Francisco Garcia-Herrero, Mehdi Mhalla, Valentin Savin, Javier Valls
2023 J jnl
Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links.
Sensors
Pau Salvador, Vicenç Almenar, Juan Luis Corral, Javier Valls, María José Canet
2021 J jnl
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes.
IEEE Access
Javier Valls, Francisco Garcia-Herrero, Nithin Raveendran, Bane Vasic
2019 J jnl
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap.
Javier Valls, Vicente Torres, María José Canet, Francisco Miguel Garcia-Herrero
2019 J jnl
FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems.
Microprocess. Microsystems
Julián S. Bruno, Vicenç Almenar, Javier Valls
2019 J jnl
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.
Circuits Syst. Signal Process.
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Garcia-Herrero
2019 J jnl
Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes.
Circuits Syst. Signal Process.
J. M. Català-Pérez, Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls, David Declercq
2018 C conf
High-Throughput One-Channel RS(255, 239) Decoder.
DSD
Gabriele Perrone, Javier Valls, Vicente Torres, Francisco Miguel Garcia-Herrero
2018 — conf
Multidimensional Multiplexing in Multicore Fibre for Hybrid Optical Backhaul provision: The XCORE Approach.
ICTON
Roberto Llorente, Maria Morant, Julián S. Bruno, Vicenç Almenar, Juan Luis Corral, Jose M. Fuster, Javier Valls
2018 — conf
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).
NEWCAS
Vicente Torres, Javier Valls, María José Canet, Francisco Garcia-Herrero
2017 J jnl
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number.
IEEE Trans. Very Large Scale Integr. Syst.
Vicente Torres, Javier Valls
2017 J jnl
Fast- and Low-Complexity atan2(a, b) Approximation [Tips and Tricks].
IEEE Signal Process. Mag.
Vicente Torres, Javier Valls, Richard G. Lyons
2016 J jnl
High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
2016 J jnl
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls
2015 C conf
A 630 Mbps non-binary LDPC decoder for FPGA.
ISCAS
Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual
2015 J jnl
Low-Complexity Time Synchronization Algorithm for Optical OFDM PON System Using a Directly Modulated DFB Laser.
JOCN
Julián S. Bruno, Vicenç Almenar, Javier Valls, Juan L. Corral
2015 J jnl
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls
2015 J jnl
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Jesus Omar Lacruz, Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 — conf
A symbol flipping decoder for NB-LDPC relying on multiple votes.
ISTC
Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 J jnl
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain.
Int. J. Reconfigurable Comput.
Guillermo A. Jaquenod, Javier Valls, Javier Siman
2014 J jnl
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, Erbao Li, David Declercq, Javier Valls
2014 J jnl
Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes.
IEEE Commun. Lett.
Francisco Garcia-Herrero, David Declercq, Javier Valls
2014 J jnl
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, María José Canet, Javier Valls
2014 J jnl
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fabian Angarita, Javier Valls, Vicenç Almenar, Vicente Torres-Carot
2014 J jnl
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree.
IEEE Commun. Lett.
J. M. Català-Pérez, Francisco Garcia-Herrero, Javier Valls, K. Liu, Shu Lin
2013 J jnl
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.
Circuits Syst. Signal Process.
Francisco Garcia-Herrero, María José Canet, Javier Valls
2013 — conf
High-speed NB-LDPC decoder for wireless applications.
ISPACS
Francisco Garcia-Herrero, Ma José Canet, Javier Valls
2013 Misc conf
Low latency T-EMS decoder for non-binary LDPC codes.
ACSSC
Erbao Li, Francisco Garcia-Herrero, David Declercq, Kiran K. Gunnam, Jesus Omar Lacruz, Javier Valls
2012 — conf
Decoder for an enhanced serial generalized bit flipping algorithm.
ICECS
Francisco Garcia-Herrero, María José Canet, Javier Valls
2012 J jnl
FPGA implementation of an OFDM-based WLAN receiver.
Microprocess. Microsystems
María José Canet, Javier Valls, Vicenç Almenar, José Marín-Roig
2012 — conf
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.
ICECS
Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls
2012 J jnl
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method.
IEEE Trans. Circuits Syst. II Express Briefs
Roberto Gutiérrez, Vicente Torres-Carot, Javier Valls
2012 J jnl
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher
2012 — conf
High-throughput FPGA-based emulator for structured LDPC codes.
ICECS
Fabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls
2012 J jnl
Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes.
J. Signal Process. Syst.
Fabian Angarita, Trinidad Sansaloni, María José Canet, Javier Valls
2012 J jnl
Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles.
J. Signal Process. Syst.
María José Canet, Vicenc Almenar-Terre, Santiago J. Flores, Javier Valls
2012 J jnl
Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation.
IET Commun.
Fabian Angarita, José Marín-Roig, Vicenç Almenar, Javier Valls
2012 J jnl
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes.
J. Signal Process. Syst.
Fabian Angarita, Trinidad Sansaloni, Asuncion Perez-Pascual, Javier Valls
2012 J jnl
Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.
IEEE Commun. Lett.
Francisco Garcia-Herrero, María José Canet, Javier Valls, Mark F. Flanagan
2011 J jnl
High-Speed RS(255, 239) Decoder Based on LCC Decoding.
Circuits Syst. Signal Process.
Francisco Garcia-Herrero, Javier Valls, Pramod Kumar Meher
2011 J jnl
Low Cost Hardware Implementation of Logarithm Approximation.
IEEE Trans. Very Large Scale Integr. Syst.
Roberto Gutiérrez, Javier Valls
2009 J jnl
50 Years of CORDIC: Algorithms, Architectures, and Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
2009 J jnl
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.
J. Signal Process. Syst.
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
2009 J jnl
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems.
J. Signal Process. Syst.
A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls
2009 B conf
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.
FPL
Roberto Gutiérrez, Javier Valls, Asuncion Perez-Pascual
2009 J jnl
Low-Power FPGA-Implementation of
J. Signal Process. Syst.
Roberto Gutiérrez, Javier Valls
2009 J jnl
Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN.
J. Circuits Syst. Comput.
Fabian Angarita, Ma José Canet, Trinidad Sansaloni, Vicenç Almenar, Javier Valls
2008 — conf
64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm.
ICECS
José Marín-Roig, Vicenç Almenar, Javier Valls, Ma José Canet
2008 J jnl
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.
J. Signal Process. Syst.
Fabian Angarita, Ma José Canet, T. Sansaloni, Javier Valls, Vicenc Almenar-Terre
2008 J jnl
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.
J. Signal Process. Syst.
Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls
2007 — conf
Design of an efficient digital down-converter for a SDR-based DVB-S receiver.
ECCTD
A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls
2007 J jnl
FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices.
IEEE Trans. Educ.
Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres-Carot, Vicenç Almenar, José F. Toledo, Javier Valls
2007 B conf
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.
FPL
Roberto Gutiérrez, Javier Valls
2007 — conf
Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard.
EUSIPCO
Ma José Canet, Vicenç Almenar, Santiago J. Flores, Javier Valls
2007 J jnl
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
J. VLSI Signal Process.
T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls
2007 B conf
Time Synchronization for the IEEE 802.11a/g WLAN Standard.
PIMRC
María José Canet, Vicenç Almenar, José Marín-Roig, Javier Valls
2006 — conf
Design of high performance timing recovery loops for communication applications.
SiPS
Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls
2006 J jnl
The use of CORDIC in software defined radios: a tutorial.
IEEE Commun. Mag.
Javier Valls, Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres, Vicenç Almenar
2005 B conf
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
FPL
Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
2005 — conf
Performance evaluation of fine time synchronizers for WLANs.
EUSIPCO
Ma José Canet, Ian J. Wassell, Javier Valls, Vicenç Almenar
2005 B conf
Statistical Power Estimation for FPGA.
FPL
Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo
2004 B conf
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems.
PIMRC
Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima
2004 A conf
Power analysis and estimation tool integrated with XPOWER.
FPGA
Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls
2003 J jnl
Digit-Serial Complex-Number Multipliers on FPGAs.
J. VLSI Signal Process.
T. Sansaloni, Javier Valls, Keshab K. Parhi
2003 J jnl
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers.
IEEE Trans. Circuits Syst. II Express Briefs
Javier Valls, Eduardo I. Boemo
2002 J jnl
Evaluation of CORDIC Algorithms for FPGA Design.
J. VLSI Signal Process.
Javier Valls, Martin Kuhlmann, Keshab K. Parhi
2002 — conf
FPGA-based radix-4 butterflies for HIPERLAN/2.
ISCAS (3)
A. Perez-Pascual, T. Sansaloni, Javier Valls
2001 — conf
Distributed arithmetic radix-2 butterflies for FPGA.
ICECS
T. Sansaloni, A. Perez-Pascual, Javier Valls
2001 — conf
FPGA based on-line complex-number multipliers.
ICECS
A. Perez-Pascual, T. Sansaloni, Javier Valls
2000 C conf
FPGA-based digit-serial complex number multiplier-accumulator.
ISCAS
Trinidad Sansaloni, Javier Valls, Keshab K. Parhi
1999 — conf
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation.
ICECS
Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo
1999 — conf
Efficient complex-number multipliers mapped on FPGA.
ICECS
A. Perez-Pascual, Javier Valls, Marcos M. Peiró
1999 — conf
Fast FPGA-based pipelined digit-serial/parallel multipliers.
ISCAS (1)
Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo
1998 — conf
Design and FPGA implementation of digit-serial FIR filters.
ICECS
Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo