Javier Resano

45 papers A* 1A 2B 4C 1Misc 1Journal 24Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores.
IEEE Trans. Circuits Syst. Artif. Intell.
Samuel Pérez Pedrajas, Javier Resano, Darío Suárez Gracia
2025 — conf
Go Fast: GPU Optimizer for FPGA-LUT Approximate Simulation and Tuning.
SBESC
Olavo A. B. Silva, Isabela Freitas, Pedro Coura, José Augusto Miranda Nacif, Ricardo Ferreira, Adrián Alcolea, María Villarroya-Gaudó, Javier Resano
2022 J jnl
Bayesian Neural Networks to Analyze Hyperspectral Datasets Using Uncertainty Metrics.
IEEE Trans. Geosci. Remote. Sens.
Adrián Alcolea, Javier Resano
2022 J jnl
GPU-Friendly Neural Networks for Remote Sensing Scene Classification.
IEEE Geosci. Remote. Sens. Lett.
Juan Mario Haut, Adrián Alcolea, Mercedes Eugenia Paoletti, Javier Plaza, Javier Resano, Antonio Plaza
2020 J jnl
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Adrián Alcolea Morena, Javier Olivito, Javier Resano, Hortensia Mecha
2020 J jnl
Inference in Supervised Spectral Classifiers for On-Board Hyperspectral Imaging: An Overview.
Remote. Sens.
Adrián Alcolea, Mercedes Eugenia Paoletti, Juan Mario Haut, Javier Resano, Antonio Plaza
2019 — conf
Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.
WCAE@ISCA
Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
2018 J jnl
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
IET Comput. Digit. Tech.
Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano
2017 J jnl
Accelerating Board Games Through Hardware/Software Codesign.
IEEE Trans. Comput. Intell. AI Games
Javier Olivito, Javier Resano, José Luis Briz
2016 J jnl
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, Javier Resano
2015 J jnl
Performance and energy efficiency analysis of a Reversi player for FPGAs and General Purpose Processors.
Microprocess. Microsystems
Javier Olivito, Ruben Gran, Javier Resano, Carlos González, Enrique F. Torres
2014 J jnl
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems.
ACM Trans. Embed. Comput. Syst.
Juan Antonio Clemente, Javier Resano, Daniel Mozos
2014 — conf
An improved FPGA-based specific processor for Blokus Duo.
FPT
Javier Olivito, Alberto Delmas, Javier Resano
2014 J jnl
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Juan Antonio Clemente, Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
2013 — conf
An FPGA-based specific processor for Blokus Duo.
FPT
Javier Olivito, Carlos González, Javier Resano
2013 J jnl
The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends.
Proc. IEEE
Sebastián López, Tanya Vladimirova, Carlos González, Javier Resano, Daniel Mozos, Antonio Plaza
2013 J jnl
Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing.
Integr.
Carlos González, Sergio Sánchez, Abel Paz, Javier Resano, Daniel Mozos, Antonio Plaza
2012 J jnl
FPGA Implementation of Abundance Estimation for Spectral Unmixing of Hyperspectral Data Using the Image Space Reconstruction Algorithm.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.
Carlos González, Javier Resano, Antonio Plaza, Daniel Mozos
2012 J jnl
FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis.
IEEE Trans. Geosci. Remote. Sens.
Carlos González, Daniel Mozos, Javier Resano, Antonio Plaza
2011 J jnl
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Juan Antonio Clemente, Javier Resano, Carlos González, Daniel Mozos
2011 — conf
A Replacement Technique to Maximize Task Reuse in Reconfigurable Systems.
IPDPS Workshops
Juan Antonio Clemente, Daniel Mozos, Javier Resano
2011 C conf
Mini workshop - Real World Engineering Projects: Discovery-based curriculum modules for first-year students.
FIE
Stephen Williams, Masoud Agah, Luiz A. DaSilva, Kamyar Dezhgosha, Allen B. MacKenzie, Nicky Mostert-Phipps, Sanjay Raman, Javier Resano
2010 J jnl
A task graph execution manager for reconfigurable multi-tasking systems.
Microprocess. Microsystems
Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos
2010 J jnl
FPGA Implementation of the Pixel Purity Index Algorithm for Remotely Sensed Hyperspectral Image Analysis.
EURASIP J. Adv. Signal Process.
Carlos González, Javier Resano, Daniel Mozos, Antonio Plaza, David Valencia
2010 — conf
FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images.
ERSA
Carlos González, Daniel Mozos, Javier Resano, Antonio Plaza
2010 — conf
FPGA implementation of a strong Reversi player.
FPT
Javier Olivito, Carlos González, Javier Resano
2009 B conf
FPGA support for satellite computations of hyper spectral images.
FPL
Carlos González, Daniel Mozos, Javier Resano
2008 — conf
A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems.
ReConFig
Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos
2008 J jnl
Efficiently scheduling runtime reconfigurations.
ACM Trans. Design Autom. Electr. Syst.
Javier Resano, Juan Antonio Clemente, Carlos González, Daniel Mozos, Francky Catthoor
2007 J jnl
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware
CoRR
Javier Resano, Daniel Mozos, Francky Catthoor
2007 — conf
HW implementation of an execution manager for reconfigurable systems.
ERSA
Javier Resano, Juan Antonio Clemente, Carlos González, Jose Luis Garcia, Daniel Mozos
2007 J jnl
Memory hierarchy for high-performance and energyaware reconfigurable systems.
IET Comput. Digit. Tech.
Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
2007 — conf
Reducing the reconfiguration overhead: a survey of techniques.
ERSA
Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
2006 B conf
A Dual Cache for Performance and Energy Aware Reconfigurable HW.
FPL
Elena Perez Ramo, Javier Resano
2006 A conf
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.
IPDPS
Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
2005 A conf
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware.
DATE
Javier Resano, Daniel Mozos, Francky Catthoor
2005 J jnl
A Reconfiguration Manager for Dynamically Reconfigurable Hardware.
IEEE Des. Test Comput.
Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor
2004 B conf
A Specific Scheduling Flow for Dynamically Reconfigurable Hardware.
FPL
Javier Resano
2004 J jnl
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocess. Microsystems
Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
2004 A* conf
Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware.
DAC
Javier Resano, Daniel Mozos
2003 — conf
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
PATMOS
Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
2003 J jnl
Analyzing communication overheads during hardware/software partitioning.
Microelectron. J.
Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
2003 Misc conf
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
FCCM
Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
2003 B conf
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
FPL
Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor
2003 — conf
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
ESTIMedia
Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor