Javier Mora

15 papers B 2Misc 1Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2019 Misc conf
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems.
FCCM
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2019 J jnl
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming.
Genet. Program. Evolvable Mach.
Javier Mora, Rubén Salvador, Eduardo de la Torre
2018 J jnl
Accelerating the evolution of a systolic array-based evolvable hardware system.
Microprocess. Microsystems
Javier Mora, Eduardo de la Torre
2018 — conf
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado.
ReConFig
Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2015 — conf
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs.
ReCoSoC
Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays.
IPDPS Workshops
Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A noise-agnostic self-adaptive image processing application based on evolvable hardware.
DASIP
Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013 — conf
A scalable evolvable hardware processing array.
ReConFig
Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 B conf
A self-adaptive image processing application based on evolvable and scalable hardware.
FPL
Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013 — conf
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform.
DASIP
Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013 J jnl
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing.
IEEE Trans. Computers
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012 B conf
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration.
FPL
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011 — conf
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems.
AHS
Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011 — conf
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support.
AHS
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011 — conf
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems.
ReConFig
Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo